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| 1 ?2018 integrated device technology, inc. january 31, 2018 description the 8t49n287 has two independent, f ractional-feedback plls that can be used as jitter attenuators and fre quency translators. it is equipped with six integer and two fractional output dividers, a llowing the generation of up to 8 differe nt output frequencies, ranging from 8khz to 1ghz. four of these frequencies are completely independ ent of each other and the inputs. th e other four are related freque ncies. the eight outputs may select a mong lvpecl, l vds, hcsl, or lvcmos output levels. this makes it ideal to be used in any frequency translation application, including 1g, 10g, 40g and 100g synchronous ethern et, otn, and sonet/sdh, including itu-t g.709 (2009) fec rates. the device may also behave a s a frequency synthesizer. the 8t49n287 accepts up to two d ifferential or single-ended inp ut clocks and a crystal input. each of the two inter nal plls can l ock to different input clocks which may be of independent frequencies. each pll can use the other input for redundant ba ckup of the primary clock, but in this case, both input clocks must be related in f requency. the device supports hitless reference switching between input c locks. the device monitors all input clocks for loss of signal (los), and generates an alarm when an input clock failure is detected. aut omatic and manual hitless reference switching options are supported. l os behavior can be set to support gapped or u n-gapped clocks. the 8t49n287 supports holdover for each pll. the holdover has a n initial accuracy of 50ppb from the point where the loss of all applicable input reference(s) has been detected. it maintains a historical average operating point for each pll that may be ret urned to in holdover at a limited phase slope. the device places no constraints on input to output frequency c onver - sion, supporting all fec rates, including the new revision of i tu-t rec - ommendation g.709 (2009), most with 0ppm conversion error. each pll has a register-selecta ble loop bandwidth from 1.4hz to 360hz. each output supports individual p hase delay settings to allow output-output alignment. the device supports output enable inputs and lock, holdover and los status outputs. the device is programmable through an i 2 c interface. it also supports i 2 c master capability to allow the register configur ation to be r ead from an exte rnal eeprom. typical applications ? otn or sonet / sdh equipment line cards (up to oc-192, and supporting fec ratios) ? otn de-mapping (gapped clock and dco mode) ? gigabit and terabit ip switches / routers including support of synchronous ethernet ? synce (g.8262) applications ? wireless base station baseband ? data communications ? 100g ethernet features ? supports sdh/sonet and sync hronous ethernet clocks including all fec rate conversions ? <0.3ps rms typical jitter (inc luding spurs), 12khz to 20mhz ? operating modes: locked to input signal, holdover and free-run ? initial holdover accuracy of 50ppb ? accepts up to two l vpecl, lvds, lvhstl, hcsl, or lvcmos input clocks ? accepts frequencies ranging from 8khz up to 875mhz ? auto and manual input clock sele ction with hit less switching ? clock input monitoring, incl uding support for gapped clocks ? phase-slope limiting and fully hitless switching options to control output phase transients ? operates from a 10mhz to 40m hz fundamental-mode crystal ? generates 8 lvpecl / lvds / hcsl or 16 lvcmos output clocks ? output frequencies ranging fro m 8khz up to 1.0ghz (diff) ? output frequencies ranging fro m 8khz to 250mhz (lvcmos) ? four general purpose i/o pins wi th optional support for status & control: ? four output enable control inputs may be mapped to any of the eight outputs ? lock, holdover and loss-of-signal status outputs ? open-drain interrupt pin ? nine programmable loop bandwidth settings for each pll from 1.4hz to 360hz ? optional fast lock function ? programmable output phase dela ys in steps as small as 16ps ? register programmable through i 2 c or via external i 2 c eeprom ? bypass clock paths for system tests ? power supply modes ? v cc / v cca / v cco ? 3.3v / 3.3v / 3.3v ? 3.3v / 3.3v / 2.5v ? 3.3v / 3.3v / 1.8v (lvcmos) ? 2.5v / 2.5v / 3.3v ? 2.5v / 2.5v / 2.5v ? 2.5v / 2.5v / 1.8v (lvcmos) ? -40c to 85c ambient operating temperature ? package: 56qfn, lead-free (rohs 6) 8t49n287 datasheet femtoclock ? ng octal universal frequency translator
2 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 7 1 % o r f n ' l d j u d p intn output divider intn output divider fracn output divider fracn output divider fractional feedback apll 0 fractional feedback apll 1 input clock monitoring, priority, & selection status registers control registers gpio logic lock 0 holdover 0 lock 1 holdover 1 osc xtal p0 clk0 otp i 2 c master i 2 c slave reset logic sclk sdata serial eeprom los q0 q1 q2 q3 q4 q5 q6 q7 p1 clk1 nint intn intn intn intn sa0 pll_byp 4 gpio nrst figure 1 t4n27 func tional block diagra 56-pin, 8mm x 8mm vfqfn package nq1 q1 v cco1 nrst nq0 q0 v cco0 nint v cca cap0_ref cap0 pll_byp v cca nq2 q2 v cco2 gpio[0] q3 v cco3 gpio[1] v cca cap1_ref cap1 v cc v cca v cca v cca v cca v cca osci osco s_a0 v ee clk0 nclk0 clk1 nclk1 v cc sdata sclk v cca nq3 gpio[2] v cco4 q4 nq4 v cco5 q5 nq5 v cco6 q6 nq6 v cco7 q7 nq7 gpio[3] 8t49n287 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 89 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 3 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 3 l q $ v v l j q p h q w ) l j x u h 3 l q r x w ' u d z l q j 4 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet pin description and pin characteristic tables table 1. pin descriptions number name type description 3 osci i crystal input. accepts a 10mhz-4 0mhz reference from a clock osc illator or a 12pf fundamental mode, parallel-resonant crystal. 4oscoo crystal output. this pin should be connected to a crystal. if a n oscillator is connected to osci, then this p in must be left unconnected. 5 s_a0 i pulldown i 2 c lower address bit a0. 12 sdata i/o pullup i 2 c interface bi-directional data. 13 sclk i/o pullup i 2 c interface bi-directional clock. 7 clk0 i pulldown non-inverting differential clock input. 8nclk0i pullup / pulldown inverting differential clock input. v cc /2 when left floating (set by the internal pullup and pulldown resistors.) 9 clk1 i pulldown non-inverting differential clock input. 10 nclk1 i pullup / pulldown inverting differential clock input. v cc /2 when left floating (set by the internal pullup and pulldown resistors.) 48, 47 q0, nq0 o universal output clock 0. please refer to the output drivers section for more details. 44, 43 q1, nq1 o universal output clock 1. please refer to the output drivers section for more details. 27, 28 q2, nq2 o universal output clock 2. please refer to the output drivers section for more details. 23, 24 q3, nq3 o universal output clock 3. please refer to the output drivers section for more details. 40, 39 q4, nq4 o universal output clock 4. please refer to the output drivers section for more details. 37, 36 q5, nq5 o universal output clock 5. please refer to the output drivers section for more details. 34, 33 q6, nq6 o universal output clock 6. please refer to the output drivers section for more details. 31, 30 q7, nq7 o universal output clock 7. please refer to the output drivers section for more details. 46 nrst i pullup master reset input. lvttl / lvcmos interface levels: 0 = all register s and state machines are reset to their default values 1 = device runs normally 50 nint o open-drain with pullup interrupt output. 29, 42, 21, 25 gpio[3:0] i/o pullup general-purpose input-outputs. lv ttl / lvcmos inpu t levels open -drain output. pulled-up with 5.1k ? resistor to v cc. 54 pll_byp i pulldown bypass selection. allow input r eferences to bypass both plls. ? lvttl / lvcmos i nterface levels. 6, epad v ee power negative supply voltage. all v ee pins and epad must be connected before any positive supply voltage is applied. 11 v cc power core and digital f unctions supply voltage. 17 v cc power core and digital f unctions supply voltage. 2 v cca power analog functions supply voltage for core analog functions. 14, 15, 16, 20 v cca power analog functions supply volt age for analog functions assoc iated with pll1. 1, 51, 55, 56 v cca power analog functions supply volt age for analog functions assoc iated with pll0. 49 v cco0 power high-speed output supply v oltage for outpu t pair q0, nq0. 45 v cco1 power high-speed output supply v oltage for outpu t pair q1, nq1. 26 v cco2 power high-speed output supply v oltage for outpu t pair q2, nq2. 22 v cco3 power high-speed output supply v oltage for outpu t pair q3, nq3. 5 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet note: pullup and pulldown refer to internal input resistors. see table 2 , pin characteristics, for typical values. table 2. pin characteristics, v cc = v ccox = 3.3v5% or 2.5v5% note: v ccox denotes: v cco0, v cco1, v cco2, v cco3, v cco4, v cco5, v cco6, v cco7. ? note 1: this specification does no t apply to osci and osco pins . 41 v cco4 power high-speed output supply v oltage for outpu t pair q4, nq4. 38 v cco5 power high-speed output supply v oltage for outpu t pair q5, nq5. 35 v cco6 power high-speed output supply v oltage for outpu t pair q6, nq6. 32 v cco7 power high-speed output supply v oltage for outpu t pair q7, nq7. 53 52 cap0, cap0_ref analog pll0 external capacitance. 18 19 cap1, cap1_ref analog pll1 external capacitance. symbol parameter test conditio ns minimum typical maximum units c in input capacitance; note 1 3.5 pf r pullup internal pullup resistor nrst, ? sdata, sclk 51 k ? nint 50 k ? gpio[3:0] 5.1 k ? r pulldown internal pulldown resistor 51 k ? c pd power dissipation capacitance (per output pair) lvcmos; ? q[0:1], q[4:7] v ccox = 3.465v 14.5 pf lvcmos q[2:3] v ccox = 3.465v 18.5 pf lvcmos; ? q[0:1], q[4:7] v ccox = 2.625v 13 pf lvcmos; q[2:3] v ccox = 2.625v 17.5 pf lvcmos; ? q[0:1], q[4:7] v ccox = 1.89v 12.5 pf lvcmos; q[2:3] v ccox = 1.89v 17 pf lvds, hcsl or lvpecl; ? q[0:1], q[4:7] v ccox = 3.465v or 2.625v 2 pf lvds, hcsl or lvpecl; q[2:3] v ccox = 3.465v or 2.625v 4.5 pf r out output ? impedance gpio [3:0] output high 5.1 k ? output low 25 ? lvcmos; ? q[0:7], nq[0:7] 20 ? number name type description 6 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet principles of operation the 8t49n287 has two plls that can each independently be locked to any of the input clocks and generate a wide range of synchro nized output clocks. it incorporates two completely independent plls. these could be used for example in the transmi t and receive pat h of synchronou s ethernet equipment. either of the input clocks can be selected as the reference for either pll. from the output of the two plls a wid e range of output frequencies can be simultaneously generated. the 8t49n287 accepts up to two di fferential input clocks rangin g from 8khz up to 875mhz. it gene rates up to eight output clocks ranging from 8kh z up to 1.0ghz. each pll path within the 8t49n2 87 supports three states: lock, holdover and free-run. lock & holdover status may be monitored on register bits and pins. each pll also supports automatic and ma nual hitless reference switching. in the locked state, the pll locks to a valid clock input and its outpu t clocks have a frequency accura cy equal to the frequency accuracy of the input clock. in the hold over state, the pll will output a cl ock which is based on the select ed holdover behavior. each of the pl l paths within the 8t49n287 ha s an initial holdover frequency offset of 50ppb. in the free-run state, the pll outputs a clock with t he same frequency accuracy as the external crystal. upon power up, each pll will enter free-run state, in this stat e it generates output clocks with the same frequ ency accuracy as the external crystal. the 8t49n287 continuously monitors each input for activity (signal transitions). in automatic reference switchin g, when an input clock has been validated the pll will transition to the locked st ate. if the s elected input clock fails and there are no other valid input clocks, th e pll will quickly detect that a nd go into holdover. in the holdover state , the pll will output a clock which is based on the selected holdover behavior. if the selected input clock fails and another input c lock is available then the 8t49n287 will hitlessly switch to that input clock. the reference switch can be either reverti ve or non-revertive. the device supports conversion of any input fr equency to four different, independent output fre quencies on the q[0:3]outputs. additionally, a further four o utput frequencies may be generate d that are integer-related to the four independent frequencies. these additional four frequencies are on the q[4:7] outputs. the 8t49n287 has a programmabl e loop bandwidth from 1.4hz to 360hz. the device monitors all input cl ocks and generates an alarm whe n an input clock failu re is detected. the device supports programm able individual output phase adjustments in order to allow c ontrol of input to output phase adjustments and output to output phase alignment. the device is program mable through an i 2 c and may also autonomously read its register set tings from an internal one-ti me programmable (otp) memory or an external serial i 2 c eeprom. crystal input the crystal input on the 8t49n287 is capable of being driven by a parallel-resonant, fundamental mode crystal with a frequency ra nge of 10mhz - 40mhz. the oscillator input also suppor ts being driven by a single-end ed crystal oscillator or reference clock. the initial holdover frequency offset is set by the device, but the long term drift depends on the quality of the crystal or oscillator attached to this port. bypass path for system test purposes, each of pll0 and pll1 may be bypassed . when pll_byp is asserted the clk0 input reference will be presented directly on the q4 out put. the clk1 input reference w ill be presented directly on the q5 output. additionally, clk0 or clk1 may be used as a clock source for th e output dividers of q[4:7]. this may only be done for input freq uencies of 250mhz or less. input clock selection the 8t49n287 a ccepts up to two input c locks with f requencies ranging from 8khz up to 875mhz. each in put can accept lvpecl, lvds, lvhstl, hcsl or lvcmos i nputs using 1.8v, 2.5v or 3.3v logic levels. to use lvcmos input s, refer to the application no te, wiring the differential input to accept single-ended levels for biasing instructions. the device has independent input cl ock selection control for ea ch pll. in manual mode, only one o f these inputs may be chosen per pll and if that input fails t hat pll will enter holdover. manual mode may be operated by directly selecting the desired i nput reference in the refsel register field. it may also operate via pin-selection of the desired inp ut clock by selecting that mode in the refsel register field. in that case, gpios must be used as cloc k select inputs (cseln). csel0 = 0 will select the clk0 input and csel0 = 1 will select the clk1 input for pll0. csel1 will perfo rm the same function for pll1. in addition, the crystal frequency may be passed directly to th e output dividers for q[4:7] for use as a reference. inputs do not support transmission of spread-spectrum clocking sources. since this family is i ntended for high-performance applications, it will assume inp ut reference sources to have st abilities of + 100ppm or better, except where g apped clock inputs are used. if the pll is working in automat ic mode, then each of the input reference sources is assigned a priority of 1-2. at power-up or if the currently selected input referenc e fails, the pll will switch t o the highest priority input reference that is valid at that time (se e input clock monitor section for details). automatic mode has two sub-options : revertive or non-revertive. in revertive mode, the pl l will switch to a reference with a highe r priority setting whenever one bec omes valid. in non-revertive m ode the pll remains with the currently select ed source as long as i t remains valid. the clock input selection is based on the input clock priority set by the clock input priorit y control registers. it is recommended t hat all input references for a pll be given different priority settings in the clock input priority contr ol registers for that pll. 7 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet input clock monitor each clock input is mo nitored for loss of signal (los). if no a ctivity has been detected on the clock input within a user-selectable t ime period then the clock input is considered to be failed and an i nternal loss-of-signal status flag is se t, which may cause an input switchover depending on other settings. the user-selectable tim e period has sufficient range to a llow a gapped clock missing man y consecutive edges to be c onsidered a valid input. user-selection of the clock monitor time-period is based on a c ounter driven by a monitor clock. the monitor clock is fixed at the fr equency of pll0s vco divided by 8. with a vco range of 3ghz - 4ghz, th e monitor clock has a frequency range of 375mhz to 500mhz. the monitor logic for each input reference will count the numbe r of monitor clock edges indicated in the appropriate monitor contro l register. if an edge is received on the input reference being monitored, then the count resets and begins again. if the targe t edge count is reached before an input r eference edge is received, th en an internal soft alarm is raised and the count re-starts. during t he soft alarm period, the pll(s) tracking this input will not be adjust ed. if an input reference edge is received before the count expires for t he second time, then the soft alarm status is cleared and the pll( s) will resume adjustments. if the coun t expires again without any inpu t reference edge being received, th en a loss-of-signal alarm is declared. it is expected that f or normal (non-gapped) clock operation, us ers will set the monitor clock count for each input reference to be slig htly longer than the nominal period of that inpu t reference. a margi n of 2-3 monitor clock periods should give a reasonably quick reacti on time and yet prevent false alarms. for gapped clock operation, the user will set the monitor clock count to a few monitor clock periods longer than the longest expected clock gap period. the monitor count r egisters support 17-bit count va lues, which will support at least a gap length of two clock periods f or any supported input reference frequ ency, with longer gaps being supported for faster input refer ence frequencies. since gapped clocks usually occur on input reference frequencies above 100mh z, gap lengths of thousands of periods can be supported. using this configuration for a gapped clock, the pll will conti nue to adjust while the normally expect ed gap is present , but will fre eze once the expected gap length has been exc eeded and alarm after twice the normal gap length has passed. once a los on any of the input clocks is detected, the appropri ate internal los alarm w ill be asserted and it will remain asserted until that input clock returns and will be validated by the receipt o f 8 rising clock edges on that input refer ence. if another error condition on the same input clock is detected during the validation time then th e alarm remains asserted a nd the validation time starts over. each los flag may al so be reflected on one of the gpio[3:0] outputs. changes in status of any reference can also generate a n interrupt if not masked. holdover 8t49n287 supports a small initial holdover frequency offset for each pll path in non-gapped clock mode. when the input clock monitor is set to support gapped clock operation, this initial holdover fr equency offset is indeterminate since t he desired behavior with gapped clocks is for the pll to continue to adj ust itself even if clock edges are missing. in gapped clock mode, th e pll will not enter holdover until the input is missing for two los monitor periods. the holdover performance characte ristics of a clock are referre d as its accuracy and stability, and are characterized in terms of t he fractional frequency offset. the 8t49n287 can only control the initial frequency accuracy. longer-term accuracy and stability are determined by the accuracy and st ability of the external oscill ator. when a pll loses all valid input references, it will enter the holdover state. in non-gapped clock mode, t he pll will initially maintai n its most recent frequency offset set ting and then tr ansition at a r ate dictated by its selected phase-s lope limit setting to a frequen cy offset setting that is based on historical settings. this behavior is intended to compensate for any frequency drift that may have occurred on the input re ference before it was detected to be lost. the historical holdover va lue will have three options: ? return to center of tuning range within the vco band. ? instantaneous mode - the hold over frequency will use the dpll current frequency 1 00msec before it entered holdover. the accuracy is shown in the ac electrical characteristics , ta ble 11 a . ? fast average mode - an inte rnal iir (infinite impulse response) filter is employed t o get the frequency offset. the iir filter gives a 3 db at tenuation point corresponding to a nominal period of 20 mi nutes. the accuracy is shown in the ac electrical characteristics , ta ble 11 a . when entering holdover, each pll will set a separate internal h old alarm internally. this alarm may be read from internal status r egister, appear on the appropriate gpio pin and/or assert the nint outpu t. while a pll is in holdover, its frequency offset is now relativ e to the crystal input and so the output c locks derived from that pll wi ll be tracing their accuracy to the local oscillator or crystal. at s ome point in time, depending on the stability & accuracy of that source, the clock(s) derived from that pll will have drifted outside of the limits of the holdover state and the syste m will be considered to be in a free-run state. since this borderline is defined outside the pl l and dictated by the accuracy and sta bility of the external local cr ystal or oscillator, the 8t49n287 cannot know or influence when that transition occurs. as a result, the 8t49n287 will remain in the holdover state internally. 8 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet input to output clock frequency the 8t49n287 is designed to accept any frequency in its input r ange and generate eight different output frequencies that are indepe ndent from each other and from the in put frequencies. the internal architecture of the de vice ensures that mo st such translations will result in the exact output freque ncy specified. where exact fre quency translation is not possible, the frequency translation error wi ll be minimized. please contact idt fo r configuration software or oth er assistance in determining if a desired configuration will be su pported exactly. synthesizer mode operation the device may also act as a fr equency synthesizer with either or both pll's generating their opera ting frequency from just the c rystal input. by setting the syn_moden register bit and setting the staten[1:0] field to freerun, no input clock references are req uired to generate the desir ed output frequencies. loop filter and bandwidth when operating in synthesizer m ode as described above, the 8t49n287 has a fixed loop band width of approximately 200khz. when operating in all other modes, the following information ap plies: the 8t49n287 uses no external c omponents to support a range of loop bandwidths: 1.40625hz, 2. 8125hz, 5.625hz, 11.25hz, 22.5hz, 45hz, 90hz, 180hz or 360hz. each pll shall support separate loo p filter settings. the device supports two different loop bandwidth settings for e ach pll: acquisition and locked. the se loop bandwidths are selected from the list of options described above. if enabled, the acqui sition bandwidth is used while lock is b eing acquired to allow the pll to fast-lock. once locked the pll will use the locked bandwidth setting. if the acquisition band width setting is not used, the pll will use the locked bandwidth setting at all times. output dividers and mapping to plls the 8t49n287 will support eight output dividers that may be map ped to either pll. six of the output dividers will have intn capabi lity only (see ta ble 3 ) and the other two will support fracn division. integer output divider programming (q[0:1], q[4:7] only) each integer output divider blo ck consists of two divider stage s in a series to achieve the desired tot al output divider ratio. the f irst stage divider may be set to divide by 4, 5 or 6. the second stage of the divider may be bypassed (i.e. di vide-by-1) or programmed to any even divider ratio from 2 to 131 ,070. the total divide ratios, settings and possible output frequencies are shown in table 3. in addition, the first divider s tage for the q[4:7] outputs sup ports a bypass (i.e. divide-by-1) oper ation for some clock sources. table 3. q[0:1], q[4:7 ] output divide ratios note: above frequency ranges for q[4:7] apply when driven direc tly from pll0 or pll1. fractional output divider programming (q[2:3] only) for the fracn output dividers q[ 2:3], the output divide ratio i s given by: output divide ratio = (n.f)x2 n = integer part: 4, 5, ...(2 18 -1) f = fractional part: [0, 1, 2, ...(2 28 -1)]/(2 28 ) for integer operation of these outputs dividers, n = 3 is also supported. output divider frequency sources output dividers associ ated with the q[0:3] outputs can take the ir input frequencies from either pll0 or pll1. output dividers associ ated with the q[4:7] outputs can take the ir input frequencies from pll0, pll1, q2 or q3 output dividers, cl k0 or clk1 input frequencies or the crystal frequency. output banks outputs of the 8t49n287 are divi ded into three banks for purpos es of output skew measurement: ? q0, nq0, q1, nq1 ? q4, nq4, q5, nq5 ? q6, nq6, q7, nq7 1st-stage divide 2nd-stage divide total divide minimum f out mhz maximum f out mhz 4 1 4 750 1000 5 1 5 600 800 6 1 6 500 666.7 4 2 8 375 500 5 2 10 300 400 6 2 12 250 333.3 4 4 16 187.5 250 5 4 20 150 200 6 4 24 125 166.7 ... 4 131,070 524,280 0.0057 0.0076 5 131,070 655,350 0.0046 0.0061 6 131,070 786,420 0.0038 0.0051 9 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet output phase control on switchover when the 8t49n287 swit ches between input re ferences, enters or leaves the holdover state for either pll, there are two options on how the output phase can be controlled in thes e events: phase-slope limiting or fully hitless switch ing (sometimes called phase bui ld-out) may be selected. the swmoden bit selects which behavior is to b e followed for plln. if fully hitless switching is selected, then the output phase w ill remain unchanged under any of these condit ions. note that fully hitles s switching is not supported when external loopback is being used . fully hitless switching should not be used unless all input ref erences are in the same clock domain. not e that use of this mode may prevent an output frequency and phase from being able to trace its alignment back to a pri mary reference source. if phase-slope limiting is sel ected, then the output phase will adjust from its previous value until i t is tracking the new condition at a rate dictated by the slewn[1:0] bits. phase-slope limiting should be used if all input references are not in the same clock domain or use rs wish to retain traceability to a primary refer ence source. input-output delay control when using the 8t49n287 in exte rnal loopback or in a situation where input-output delay needs to be known and controlled, it i s necessary to examine the exact signal path through the device. due to the flexibility of the device , there are a large number of p otential signal paths from input to output through it that depend on the desired configuration. each of those po tential paths may include or exc lude logic blocks from the path and change the absolute value of the delay (static phase offset or spo) thr ough the device. considering th e range of spo values to cover all those potential p aths would no t be useful in achieving the target delays for any specific user configuration. please contact idt for the specific spo value associated with a desired input- output path. note that events s uch as switchovers, entering or leaving holdover or re-configuring the signal path can result in one-time chang es to the spo due to that path re-configuration. the ac electrical characteristics , ( table 11a ) indicates the maximum variation in spo that could be expected f or a particular path through the device. output phase alignment the device has a programmable out put to output phase alignment for each of the eight output dividers. after pow er-up and the plls have achieved lock, the device will be in a state wh ere the outputs are synchronized with a deterministic offset relative to each other . after synchronization, the output alig nment will depend on the partic ular configuration of each output acco rding to the following rules. the step size is defined a s the period of the clock to that divider : 1) only outputs derived from t he same source will be aligned wi th each other. 'source' means the ref erence selected to drive the output divider as controlled by the clk_seln bit for each output. 2) for integer dividers (q[0:1 ], q[4:7]) when both divider stag es are active, edges are aligned. this case is used as a baseline to c ompare the other cases here. 3) for integer dividers where t he 1st-stage divider is bypassed (only q[4:7] support this), coarse dela y adjustments cant be perform ed. the output phase will be one st ep earlier than in case 2. 4) fractional output dividers (q2 or q3) do not guarantee any s pecific phase on power-up or after a synchronization event. 5) integer dividers using q2 or q3 as a source (q[4:7] support this option) will be aligned to their s ource divider's output (q2 or q3). note that the output skews described above are not included in any of the phase adjustm ents described here. once the device is in operation, the outputs associated with ea ch pll may have their phase adjustments re-synced in one of two wa ys: 1) if the pll becomes unlocked, t he coarse phase adjustments wi ll be reset and the fin e phase adjustments will be re-loaded once it becomes locked again. 2) toggling of a register bit for either pll (plln_syn bits in register 00a8h) may also be us ed to force a re-sync / re-load for output s associated with that pll. the user may apply ad justments that are p roportional to the per iod of the clock source each output divider is operating from. for example, if the divider associa ted with output q3 is running of f pll0, which has a vco frequency of 4gh z, then the appropriate period would be 250ps. the output phas e may be adjust ed in these steps across the full perio d of the output. ? coarse adjustment: all output dividers may have their phase adjusted in steps of the source clock period. for example a 4gh z vco gives a step size of 250 ps. the user may request an adjustment of phase of up to 31 steps using a single register w rite. the phase will be adjusted by lengthening the period of the out put by 250ps at a time. this proce ss will be repeated every four ou tput clock periods until the full r equested adjustment has been achieved. a busy signal will rem ain asserted in the phase delay register until the requested adju stment is complete. then a fur ther adjustment may be setu p and triggered by toggling the trigger b it. ? fine adjustment: for the fraction al output dividers associated with the q2 and q3 out puts, the phase of t hose outputs may be further adjusted with a granularity of 1/16th of the vco period . for example a 4ghz vco frequency give s a granularity of 16ps. this is performed by directly writing the required offset (from the nominal rising edge position) in units of 1/16th of the output period into a register. then the app ropriate plln_syn bit must be toggled to load the new value. no te that toggling this bit will clear all coarse delays for all outputs associated with that pll, so fine delays should be set first, befor e coarse delays. the output wi ll then jump directly to that new o ffset value. for this reason, t his adjustment should be made as the input is initially programmed or in high-impedance. each output has the capability o f being inverted (180 phase sh ift). jitter and wander tolerance the 8t49n287 can be us ed as a line card device and therefore is expected to tolerate the jitter and wander output of a timing c ard pll (e.g. 82p33714). 10 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet output drivers the q0 to q7 clock outputs are p rovided with register-controlle d output drivers. by se lecting the output drive type in the appro priate register, any of these outputs c an support lvcmos, lvpecl, hcsl or lvds logic levels. the operating voltage ranges of ea ch output is det ermined by it s independent output power pin (v cco ) and thus each can have different output voltage levels. output voltage levels of 2.5v or 3.3v are supported for differential o peration and lvcmos operation. in addition, lvcmos output ope ration supports 1.8v v cco . each output may be enabled or dis abled by register bits and/or gpio pins configured as output enables. the outputs will be enabled if the register bit and the associated oe pin are both asserted (high) . when disabled an output will be in a high impedance state. lvcmos operation when a given output is configure d to provide lvc mos levels, the n both the q and nq outputs will toggle at the selected output frequency. all the previously de scribed configurat ion and contr ol apply equally to both outputs. f requency, phase alignment, volt age levels and enable / disable stat us apply to both the q and nq p ins. when configured as lvcmos, the q and nq outputs can be selected to be phase-aligned with each other or inverted relative to one another. phase-aligned outputs will have increased simultaneous switching currents w hich can negatively affect phase noise performance and power consumption. it is recommended that use o f this selection be kept to a minimum. power-saving modes to allow the device to consume t he least power possible for a g iven application, the following functi ons are included under registe r control: ? pll1 may be shut down. ? any unused output, including al l output divider and phase adjustment logic, can be individually powered-off. ? clock gating on logic that is not being used. status / control signa ls and interrupts general-purpose i/os & interrupts the 8t49n287 provides 4 general purpose input / output (gpio) pins for miscellaneous status & control functions. each gpio ma y be configured as an input or an ou tput. each gpio may be directly controlled from register bits or be used as a pred efined functi on as shown in table 4 . note that the default stat e prior to configuration being loaded from i nternal otp or external eeprom will be to se t each gpio to function as an output enable. table 4. gpio configuration if used in the fixed function mod e of operation, the gpio bits will reflect the real-time status of their respective status bits as shown in table 4 . note that the lol signal repr esents the lock status of the pll. it does not account for the process of synchronization of the output dividers associated with that pll. the output dividers programmed to operate from that pll will automatically go throu gh a re-synchronization process when the pll locks or re-locks, or i f the user triggers a re-sync manually v ia register bit plln_syn. thi s synchronization proce ss may result in a per iod of instability o n the affected outputs for a duration of up to 350ns after the re-loc k (lol de-asserts) or the plln_syn bit is de-asserted. interrupt functionality interrupt functionality includes an interrupt status flag for e ach of pll loss-of-lock status (lol[1:0]), pll holdover status (hold[1:0]) and input reference status (los[ 1:0]) that is set whenever ther e is an alarm on any of those signals. the status flag will remain s et until the alarm has been cl eared and a 1 has b een writte n to the st atus flags register location or if a reset occurs. each status flag will also have an interrupt enable bit that will determine if that status flag is allowed to cause the interrupt status to be affected (enabled) or not (disabled). all interrupt enable bits will be in the disabled s tate after reset. the device interrupt sta tus flag and nint output pin are asserted if any of t he enabled interrupt st atus flags are set. device hardware configuration the 8t49n287 supports an internal one-time programmable (otp) memory that can be pre-programmed at the factory with 1 complet e device configuration. if the device is set to read a configurat ion from an external, serial eeprom, then the values read will overwrite the otp-defined values. this configuration can be over-written using the serial interfa ce once reset is complete. any configurat ion written via the programmin g interface needs to be re-written after any power cycle or reset . please contact idt if a specific factory -programmed configuration is d esired. gpio pin configured as input configured as output fixed function general purpose fixed function general purpose output enable (default) output enable clock select 3 oe[3] oe[7] csel1 gpi[3] - - gpo[3] 2 oe[2] oe[6] csel0 gpi[2] los[0] los[1] gpo[2] 1 oe[1] oe[5] - gpi[1] hold[0] hold[1] gpo[1] 0 oe[0] oe[4] - gpi[0] lol[0] lol[1] gpo[0] 11 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet device start-up a nd reset behavior the 8t49n287 has an internal pow er-up reset (por) circuit and a master reset input pin nrst. if either is asserted, the device will be in the reset state. for highly programmable devices, it is common practice to reset the device immediately after the initial power-on sequence. idt recommends connecting the nrst input pin to a programmable logi c source for optimal functionality. it is recommended that a mini mum pulse width of 10ns be used t o drive the nrst input pin. while in the reset state (nrst i nput asserted or por active), t he device will operate as follows: ? all registers will return to & b e held in their default states as indicated in the applicab le register description. ? all internal state machines will be in their reset conditions. ? the serial interface will not r espond to read or write cycles. ? the gpio signals will be configur ed as general-purpose inputs. ? all clock outputs will be disabled. ? all interrupt status and interr upt enable bits will be cleared , negating the nint signal. upon the later of the internal p or circuit expiring or the nrst input negating, the device will exit reset and begin self-configurati on. the device will load an initial block of its internal registers using the configuration stored in the internal one-t ime programmable (otp ) memory. once this step is compl ete, the 8t49n287 will check the register settings to see if it should load the remainder of its configuration from an external i 2 c eeprom at a defined address or continue loading from otp. see the section on i 2 c boot initialization for details on how this is performed. once the full configuration has been loaded, the device will re spond to accesses on the serial port and will attempt to lock both pl ls to the selected sources and begin operation. once the plls are loc ked, all the outputs derived from a g iven pll will be synchronized a nd output phase adjustments can then be applied if desired. serial control port description serial control port configuration description the device has a serial control port capable of responding as a slave in an i 2 c compatible configuration, to allow access any of the internal registers for device programming or exami nation of internal sta tus. all registers are configured to have default values. see the sp ecifics for each register for details. the device has the additional capability of becoming a master o n the i 2 c bus only for t he purpose of reading its initial register configurations from a s erial eeprom on the i 2 c bus. writing of the configuration to the serial eepr om must be performed by another device on the same i 2 c bus or pre-programmed into the device prior to assembly. i 2 c mode operation the i 2 c interface is des igned to fully suppo rt v2.1 of the i 2 c specification for normal and fa st mode operation. the device ac ts as a slave device on the i 2 c bus at 100khz or 400khz using the address defined in the status i nterface control register (0006h ), as modified by the s_a0 input pin setting. the interface accepts byte-oriented block wr ite and block read op erations. two addres s bytes specify the register addre ss of the byte po sition of the first register to write or read. data bytes (registers) are accessed in sequential order from the lowest t o the highest byte (most sign ificant bit first). read and write block transfers can be stopped after any complete byte transfer. during a write operation, data will not be moved into the registers until the stop bit is received, at whi ch point, all data received in the block write will be written simultaneo usly. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resi stors have a size of 51k ? typical. figure 3. i 2 c slave read and writ e cycle sequencing current?read s dev?addr?+?r a data?0 a data?1 a a data?n a p sequential?read s dev?addr?+?w a data?0 a data?1 a a data?n a p offset?addr?msb a sr dev?addr?+?r a sequential?write s dev?addr?+?w a data?0 p a data?1 a a data?n a from?master?to?slave from?slave?to?master offset?addr?lsb a offset?addr?msb a offset?addr?lsb a s?=?start sr?=?repeated?start a?=?acknowledge a =?none?acknowledge p?=?stop 12 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet i 2 c master mode when operating in i 2 c mode, the 8t49n287 has the capability to become a bus master on the i 2 c bus for the purpos es of reading its configuration from an external i 2 c eeprom. only a block read cycle will be supported. as an i 2 c bus master, the 8t49n287 will support the following functions: ? 7-bit addressing mode ? base address regi ster for eeprom ? validation of the read block via ccitt-8 crc check against val ue stored in last byt e (e0h) of eeprom ? support for 100khz and 400khz operation with speed negotiation . if bit d0 is set at byte addre ss 05h in the eepr om, this will s hift from 100khz operation to 400khz operation. ? support for 1 or 2-byte addressing mode ? master arbitration with prog rammable number of retries ? fixed-period cycle response timer to prevent permanently hangi ng the i 2 c bus. ? read will abort with an alarm (b ootfail) if any of the followi ng conditions occur: slave nack, arb itration fail, collision durin g address phase, crc failure, slave response time-out ? the 8t49n287 will not suppor t the following functions: ?i 2 c general call ? slave clock stretching ?i 2 c start byte protocol ? eeprom chaining ? cbus compatibility ? responding to its own slave addr ess when acting as a master ? writing to external i 2 c devices including the external eeprom used for booting figure 4. i 2 c master read cycle sequencing sequential?read?(1\byte?offset?address) s dev?addr?+?w a data?0 a data?1 a a data?n a p sr dev?addr?+?r a offset?addr a sequential?read?(2\byte?offset?address) s dev?addr?+?w a data?0 a data?1 a a data?n a p offset?addr?msb a sr dev?addr?+?r a offset?addr?lsb a from?master?to?slave from?slave?to?master s?=?start sr?=?repeated?start a?=?acknowledge a =?none?acknowledge p?=?stop 13 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet i 2 c boot-up initialization mode if enabled (via the boot_eep bit in the startup register), once the nrst input has been de-asserted ( high) and its internal power-u p reset sequence has completed, the device will contend for owner ship of the i 2 c bus to read its initial regis ter settings from a memory location on the i 2 c bus. the address of that memory location is kept in non-volatile memory in the st artup register. during the boot -up process, the device will not resp ond to serial control port acc esses. once the initialization process is complete, the contents of an y of the devices registers can be altered. it is the responsibility of the user to make any desired adjustments in initial values directly in the serial bus memory. if a nack is received to any of the read cycles performed by th e device during the initialization process, or if the crc does no t match the one stored in address e0h of the eepr om the pro cess will be aborted and any uninitialized reg isters will remain with their default values. the bootfail bit (021eh) in the global interrupt status register will also be set in this event. if the bootfail bit is set, then both lol[n] indicators will be set. contents of the eeprom s hould be as shown in table 5 . table 5. external se rial eeprom contents eeprom offset (hex) contents d7 d6 d5 d4 d3 d2 d1 d0 00 1111111 1 01 1111111 1 02 1111111 1 03 1111111 1 04 1111111 1 05 1111111 serial eeprom speed select 0 = 100khz 1 = 400khz 06 1 8t49n287 device i 2 c address [6:2] 0 1 07 0000000 0 08 - df desired contents of device registers 08h - dfh e0 serial eeprom crc e1 - ff unused 14 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet register descriptions table 6a.register blocks register ranges offset (hex) register block description 0000 - 0001 startup control registers 0002 - 0005 device id control registers 0006 - 0007 serial interface control registers 0008 - 003a digital pll0 control registers 003b - 006d digital pll 1 control registers 006e - 0076 gpio control registers 0077 - 00ab output clo ck control registers 00ac - 00af analog pll0 control registers 00b0 - 00b3 analog pl l1 control registers 00b4 - 00b8 power-down control registers 00b9 - 00c6 input monitor control registers 00c7 interrupt enable register 00c8 - 00cb digital phase de tector control registers 00cc - 01ff reserved 1 note 1: reserved. always write 0 to this bit location. read val ues are not defined. 0200 - 0203 interrup t status registers 0204 output phase adjustment status register 0205 - 020e digital pll 0 status registers 020f - 0218 digital pll1 status registers 0219 general-purpose input status register 021a - 021f global interrupt and boot st atus register 0220 - 03ff reserved 1 15 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6b. startup control registe r bit field lo cations and desc riptions note 1: these values are specific to the device configuration a nd can be customized when ordering. refer to the femtoclock ng universal frequency translator ordering product information guide for more details. table 6c. device id control reg ister bit field locations and de scriptions note 1: these values are specific to the device configuration a nd can be customized when ordering. refer to the femtoclock ng universal frequency translator ordering product information guide or custom datasheet add endum for more details. startup control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0000 eep_rty[4:0] rsvd nboot_otp nboot_eep 0001 eep_a15 eep_addr[6:0] startup control register block field descriptions bit field name field type default value description eep_rty[4:0] r/w 00001b select number of times arbitration for the i 2 c bus to read the se rial eeprom will be retried before be ing aborted. note that th is number does not in clude the original try. nboot_otp r/w note 1 internal one-time pr ogrammable (otp) mem ory usage on power-up: 0 = load power-up conf iguration from otp 1 = only load 1st ei ght bytes from otp nboot_eep r/w note 1 external eeprom usage on power-up: 0 = load power-up configuration from external serial eeprom (ov erwrites otp values) 1 = dont use external eeprom eep_a15 r/w note 1 serial eeprom supports 15-bit a ddressing mode (multiple pages). eep_addr[6:0] r/w note 1 i 2 c base address for serial eeprom. rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. device id control registe r block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0002 rev_id[3:0] dev_id[15:12] 0003 dev_id[11:4] 0004 dev_id[3:0] dash_code [10:7] 0005 dash_code [6:0] 1 device id control register block field descriptions bit field name field type default value description rev_id[3:0] r/w 0000b device revision. dev_id[15:0] r/w 605h device id code. dash code [10:0] r/w note 1 device dash code: decimal value assigned by idt to identify the configuration loa ded at the factory. ? may be over-written by user s at any time. refer to femtoclock ng universal frequency translator ordering product information guide to identify major configuration parameters associ ated with this d ash code value. 16 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6d. serial interface contro l register bit field locations and descriptions note 1: these values are specific to the device configuration a nd can be customized when ordering. generic dash codes -900 thr ough -908, -998 and-999 are available and programmed with the default i 2 c address of 1111100b. please ref er to the femtoclock ng univer sal frequency translator ordering pr oduct information guide for mor e details. serial interface contro l block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0006 rsvd uftadd[6:2] uftadd[1] uftadd[0] 0007 rsvd 1 serial interface control regis ter block field descriptions bit field name field type default value description uftadd[6:2] r/w note 1 configurable portion of i 2 c base address (bits 6: 2) for this device. uftadd[1] r/o 0b i 2 c base address bit 1. t his bit is fi xed at 0. uftadd[0] r/o 0b i 2 c base address bit 0. this addr ess bit reflects the status of t he s_a0 external input pin. see table 1 , pin description. rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. 17 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6e. digital pll0 input con trol register bit field locatio ns and descriptions digital pll0 input control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0008 refsel0[2:0] fbsel0[1:0] rvrt0 swmode0 0009 11 10 pri0_1[1:0] pri0_0[1:0] 000a 1 1 refdis0_1 refdis0_0 rsvd rsvd state0[1:0] 000b rsvd pre0_0[20:16] 000c pre0_0[15:8] 000d pre0_0[7:0] 000e rsvd pre0_1[20:16] 000f pre0_1[15:8] 0010 pre0_1[7:0] 0011 rsvd rsvd 0012 rsvd 0013 rsvd 0014 rsvd rsvd 0015 rsvd 0016 rsvd digital pll0 input control register block field descriptions bit field name field type default value description refsel0[2:0] r/w 000b input reference select ion for digital pll0: ? 000 = automatic selection 001 = manual select ion by gpio inputs 010 through 011 = reserved 100 = force selection of input reference 0 101 = force selection of input reference 1 110 = do not use 111 = do not use fbsel0[2:0] r/w 000b feedback mode selectio n for digital pll0: ? 000 through 011 = internal feedback divider 100 = external feedback from input reference 0 101 = external feedback from input reference 1 110 = do not use 111 = do not use rvrt0 r/w 1b automatic switching mo de for digital pll0: 0 = non-revertive switching 1 = revertive switching swmode0 r/w 1b controls how digital pll0 adjusts output phase when switching b etween input references: 0 = absorb any phase differences between old and new input refe rences at the pll output. recommended for use when both inpu t references are in the same clock domain. 1 = limit the maximum rate of ph ase change at the pll output wh en adjusting to a new input references phase/frequency using phase-slope limiting as set in the slewn bits. recommended for use when the input references are not in the sa me clock domain. pri0_0[1:0] r/w 00b switchover priority for input r eference 0 when used by digital pll0: ? 00 = 1st priority ? 01 = 2nd priority ? 10 = do not use ? 11 = do not use 18 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet pri0_1[1:0] r/w 01b switchover priority for input r eference 1 when used by digital pll0: ? 00 = 1st priority ? 01 = 2nd priority ? 10 = do not use ? 11 = do not use refdis0_0 r/w 0b input reference 0 switching sele ction disable for digital pll0: ? 0 = input reference 0 is included in the switchover sequence fo r digital pll0 1 = input reference 0 is not included in the switchover sequenc e for digital pll0 refdis0_1 r/w 0b input reference 1 switching sele ction disable for digital pll0: ? 0 = input reference 1 is included in the switchover sequence fo r digital pll0 1 = input reference 1 is not included in the switchover sequenc e for digital pll0 state0[1:0] r/w 00b digital pll0 state machine control: 00 = run automatically 01 = force freerun stat e - set this if in synthesizer mode for pll0 10 = force normal state 11 = force holdover state pre0_0[20:0] r/w 000000h pre-divider ratio for input reference 0 w hen used by digital pll0. pre0_1[20:0] r/w 000000h pre-divider ratio for input reference 1 w hen used by digital pll0. rsvd r/w - reserved. alwa ys write 0 to this bi t location. read val ues are not defined. digital pll0 input control register block field descriptions bit field name field type default value description 19 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6f. digital pll0 feedback c ontrol register bit field loca tions and descriptions digital pll0 feedback control r egister block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0017 m1_0_0[23:16] 0018 m1_0_0[15:8] 0019 m1_0_0[7:0] 001a m1_0_1[23:16] 001b m1_0_1[15:8] 001c m1_0_1[7:0] 001d rsvd 001e rsvd 001f rsvd 0020 rsvd 0021 rsvd 0022 rsvd 0023 lckbw0[3:0] acqbw0[3:0] 0024 lckdamp0[2:0] acqda mp0[2:0] pllgain0[1:0] 0025 rsvd rsvd rsvd rsvd 0026 rsvd 0027 rsvd 0028 rsvd rsvd 0029 rsvd 002a rsvd 002b ffh 002c ffh 002d ffh 002e ffh 002f slew0[1:0] rsvd hold0[1:0] rsvd holdavg0 fastlck0 0030 lock0[7:0] 0031 rsvd dsm_int0[8] 0032 dsm_int0[7:0] 0033 rsvd dsmfrac0[20:16] 0034 dsmfrac0[15:8] 0035 dsmfrac0[7:0] 0036 rsvd 0037 01h 0038 rsvd 0039 rsvd 003a dsm_ord0[1:0] dcxogain0[1:0] rsvd dithgain0[2:0] 20 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet digital pll0 feedback configurat ion register block field descr iptions bit field name field type default value description m1_0_0[23:0] r/w 070000h m1 feedback divider ratio for input refer ence 0 when used by digital pll0. m1_0_1[23:0] r/w 070000h m1 feedback divider ratio for input refer ence 1 when used by digital pll0. lckbw0[3:0] r/w 0111b digital pll loop bandwidth while locked: 0000 = reserved 0001 = reserved 0010 = reserved 0011 = 1.40625hz 0100 = 2.8125hz 0101 = 5.625hz 0110 = 11.25hz 0111 = 22.5hz 1000 = 45hz 1001 = 90hz 1010 = 180hz 1011 = 360hz 1100 through 1111 = reserved acqbw0[3:0] r/w 0111b digital pll0 loop bandwidth while i n acquisition (not-locked): 0000 = reserved 0001 = reserved 0010 = reserved 0011 = 1.40625hz 0100 = 2.8125hz 0101 = 5.625hz 0110 = 11.25hz 0111 = 22.5hz 1000 = 45hz 1001 = 90hz 1010 = 180hz 1011 = 360hz 1100 through 1111 = reserved lckdamp0[2:0] r/w 011b damping factor for digital pll0 while locked: ? 000 = reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = reserved 111 = reserved acqdamp0[2:0] r/w 011b damping factor for digital pll0 while in acquisition (not locke d): ? 000 = reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = reserved 111 = reserved pllgain0[1:0] r/w 01b digital loop filter gain s ettings for digital pll0: ? 00 = 0.5 01 = 1 10 = 1.5 11 = 2 21 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet note 1: settings other than 00 m ay result in a significant in crease in initial lock time. slew0[1:0] r/w 00b phase-slope control for digital pll0: ? 00 = no limit - controlled by l oop bandwidth of digital pll0 ( note 1 ) 01 = 83 sec/sec 10 = 13 sec/sec 11 = reserved hold0[1:0] r/w 00b holdover averaging mode selection for digital pll0: 00 = instantaneous mode - uses hist orical value 100ms prior to entering holdover 01 = fast average mode 10 = reserved 11 = set vco control voltage to v cc /2 holdavg0 r/w 0b holdover averaging enable for digital pll0: 0 = holdover averaging disabled 1 = holdover averaging enabl ed as defined in hold0[1:0] fastlck0 r/w 0b enables fast lock operation for digital pll0: 0 = normal locking using lckbw0 & lckdamp0 fields in all cases 1 = fast lock mode using acqbw0 & acqdamp0 when not phase locke d and lckbw0 & lckdamp0 once phase locked lock0[7:0] r/w 3fh lock window size for digital pll0. unsigned 2s complement bina ry number in steps of 2.5ns, giving a total range o f 640ns. do not program to 0. dsm_int0[8:0] r/w 02dh integer portion of the delta-sigm a modulator value. do not set higher than ffh. this implies that for crystal frequenc ies lower than 16mhz, the doub ler circui t must be enabled. dsmfrac0[20:0] r/w 000000h fractional portion of delta-sigm a modulator valu e. divide this number by 2 21 to determine the actual fraction. dsm_ord0[1:0] r/w 11b delta-sigma modulator order for digital pll0: 00 = delta-sigma modulator disabled 01 = 1st order modulation 10 = 2nd order modulation 11 = 3rd order modulation dcxogain0[1:0] r/w 01b multiplier applied to instantane ous frequency error before it i s applied to the digitally controlled oscillator in digital pll0: 00 = 0.5 01 = 1 10 = 2 11 = 4 dithgain0[2:0] r/w 000b dither gain setting for digital pll0: 000 = no dither 001 = least significant bit (lsb) only 010 = 2 lsbs 011 = 4 lsbs 100 = 8 lsbs 101 = 16 lsbs 110 = 32 lsbs 111 = 64 lsbs rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. digital pll0 feedback configurat ion register bl ock field descr iptions bit field name field type default value description 22 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6g. digital pll1 input control regist er bit field locatio ns and descriptions digital pll1 input control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 003b refsel1[2:0] fbsel1[1:0] rvrt1 swmode1 003c 11 10 pri1_1[1:0] pri1_0[1:0] 003d 1 1 refdis1_1 refdis1_0 rsvd rsvd state1[1:0] 003e rsvd pre1_0[20:16] 003f pre1_0[15:8] 0040 pre1_0[7:0] 0041 rsvd pre1_1[20:16] 0042 pre1_1[15:8] 0043 pre1_1[7:0] 0044 rsvd rsvd 0045 rsvd 0046 rsvd 0047 rsvd rsvd 0048 rsvd 0049 rsvd digital pll1 input control regis ter block field descriptions bit field name field type default value description refsel1[2:0] r/w 000b input reference selection for digital pll1: ? 000 = automatic selection 001 = manual selection by gpio inputs 010 through 011 = reserved 100 = force selection of input reference 0 101 = force selection of input reference 1 110 = do not use 111 = do not use fbsel1[2:0] r/w 000b feedback mode selection for digital pll1: ? 000 through 011 = internal feedback divider 100 = external feedback from input reference 0 101 = external feedback from input reference 1 110 = do not use 111 = do not use rvrt1 r/w 1b automatic switching mode for digital pll1: 0 = non-revert ive switching 1 = revertive switching swmode1 r/w 1b controls how digital pll1 adjusts output phase when switching b etween input references: 0 = absorb any phase differences between old and new input refe rences at the pll output. recommended for use when both inpu t references are in the same clock domain. 1 = limit the maximum rate of phase change at t he pll output wh en adjusting to a new input references phase/frequency using phase-slope limiting as set in the slewn bits. recommended for use when the in put references are not in the sa me clock domain. pri1_0[1:0] r/w 00b switchover priority for input re ference 0 when used by digital pll1: ? 00 = 1st priority ? 01 = 2nd priority ? 10 = do not use ? 11 = do not use 23 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet pri1_1[1:0] r/w 01b switchover priority for input re ference 1 when used by digital pll1: ? 00 = 1st priority ? 01 = 2nd priority ? 10 = do not use ? 11 = do not use refdis1_0 r/w 0b input reference 0 switching sele ction disable for digital pll1: ? 0 = input reference 0 is include d in the switchover sequence fo r digital pll1 1 = input reference 0 is not included in the switchover sequenc e for digital pll1 refdis1_1 r/w 0b input reference 1 switching sele ction disable for digital pll1: ? 0 = input reference 1 is include d in the switchover sequence fo r digital pll1 1 = input reference 1 is not included in the switchover sequenc e for digital pll1 state1[1:0] r/w 00b digital pll1 state machine control: 00 = run automatically 01 = force freerun state - set thi s if in synthesizer mode for pll1 10 = force normal state 11 = force holdover state pre1_0[20:0] r/w 000000h pre-divider ratio for input reference 0 w hen used by digital pll1. pre1_1[20:0] r/w 000000h pre-divider ratio for input reference 1 w hen used by digital pll1. rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. digital pll1 input control regis ter block field descriptions bit field name field type default value description 24 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6h. digital pll1 feedback c ontrol register bit field loca tions and descriptions digital pll1 feedback control r egister block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 004a m1_1_0[23:16] 004b m1_1_0[15:8] 004c m1_1_0[7:0] 004d m1_1_1[23:16] 004e m1_1_1[15:8] 004f m1_1_1[7:0] 0050 rsvd 0051 rsvd 0052 rsvd 0053 rsvd 0054 rsvd 0055 rsvd 0056 lckbw1[3:0] acqbw1[3:0] 0057 lckdamp1[2:0] acqdamp1[2:0] pllgain1[1:0] 0058 rsvd rsvd rsvd rsvd 0059 rsvd 005a rsvd 005b rsvd rsvd 005c rsvd 005d rsvd 005e ffh 005f ffh 0060 ffh 0061 ffh 0062 slew1[1:0] rsvd hold1[1:0] rsvd holdavg1 fastlck1 0063 lock1[7:0] 0064 rsvd dsm_int1[ 8] 0065 dsm_int1[7:0] 0066 rsvd dsmfrac1[20:16] 0067 dsmfrac1[15:8] 0068 dsmfrac1[7:0] 0069 rsvd 006a 01h 006b rsvd 006c rsvd 006d dsm_ord1[1:0] dcxogain1[1:0] rsvd dithgain1[2:0] 25 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet digital pll1 feedback configurat ion register bl ock field descr iptions bit field name field type default value description m1_1_0[23:0] r/w 070000h m1 feedback d ivider ratio for input refer ence 0 when used by digital pll1. m1_1_1[23:0] r/w 070000h m1 feedback d ivider ratio for input refer ence 1 when used by digital pll1. lckbw1[3:0] r/w 0111b digital pll1 loop bandwidth while locked: 0000 = reserved 0001 = reserved 0010 = reserved 0011 = 1.40625hz 0100 = 2.8125hz 0101 = 5.625hz 0110 = 11.25hz 0111 = 22.5hz 1000 = 45hz 1001 = 90hz 1010 = 180hz 1011 = 360hz 1100 through 1111 = reserved acqbw1[3:0] r/w 0111b digital pll1 loop bandwidth while i n acquisition (not-locked): 0000 = reserved 0001 = reserved 0010 = reserved 0011 = 1.40625hz 0100 = 2.8125hz 0101 = 5.625hz 0110 = 11.25hz 0111 = 22.5hz 1000 = 45hz 1001 = 90hz 1010 = 180hz 1011 = 360hz 1100 through 1111 = reserved lckdamp1[2:0] r/w 011b damping factor for digital pll1 while locked: ? 000 = reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = reserved 111 = reserved acqdamp1[2:0] r/w 011b damping factor for digital pll1 while in acquisi tion (not locke d): ? 000 = reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = reserved 111 = reserved pllgain1[1:0] r/w 01b digital loop filter gain se ttings for digital pll1: ? 00 = 0.5 01 = 1 10 = 1.5 11 = 2 26 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet note 1: settings other than 00 m ay result in a significant in crease in initial lock time. slew1[1:0] r/w 00b phase-slope control for digital pll1: ? 00 = no limit - controlled by l oop bandwidth of digital pll0 ( note 1 ) 01 = 83 sec/sec 10 = 13 sec/sec 11 = reserved hold1[1:0] r/w 00b holdover averaging mode selection for digital pll1: 00 = instantaneous mode - uses hist orical value 100ms prior to entering holdover 01 = fast average mode 10 = reserved 11 = set vco control voltage to v cc /2 holdavg1 r/w 0b holdover averaging enable for digital pll1: 0 = holdover averaging disabled 1 = holdover averaging enabl ed as defined in hold1[1:0] fastlck1 r/w 0b enables fast lock operation for digital pll1: 0 = normal locking using lckbw1 & lckdamp1 fields in all cases 1 = fast lock mode usi ng acqbw1 & acqdamp1 when not phase locke d and lckbw1 & lckdamp1 once phase locked lock1[7:0] r/w 3fh lock window size for digital pll1. unsigned 2s complement bina ry number in steps of 2.5ns, giving a total range of 640ns. do not program to 0. dsm_int1[8:0] r/w 02dh integer portion of the delta-si gma modulator val ue. do not set higher than ffh. this implies that for crystal frequenc ies lower than 16mhz, the doub ler circui t must be enabled. dsmfrac1[20:0] r/w 000000h fractional portion of delta-sigm a modulator valu e. divide this number by 2 21 to determine the actual fraction. dsm_ord1[1:0] r/w 11b delta-sigma modulator o rder for digital pll1: 00 = delta-sigma modulator disabled 01 = 1st order modulation 10 = 2nd order modulation 11 = 3rd order modulation dcxogain1[1:0] r/w 01b multiplier applied to instantan eous frequency erro r before it i s applied to t he digitally controlled oscillator in digital pll1: 00 = 0.5 01 = 1 10 = 2 11 = 4 dithgain1[2:0] r/w 000b dither gain setting fo r digital pll1: 000 = no dither 001 = least significant bit (lsb) only 010 = 2 lsbs 011 = 4 lsbs 100 = 8 lsbs 101 = 16 lsbs 110 = 32 lsbs 111 = 64 lsbs rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. digital pll1 feedback configurat ion register bl ock field descr iptions bit field name field type default value description 27 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 7 d e o h , * 3 , 2 & r q w u r o 5 h j l v w h u % l w ) l h o g / r f d w l r q v d q g ' h v f u l s w l r q v the values observed on any gpio p ins that are us ed as general p urpose inputs are visible in t he gpi[3:0] register that is loca ted at location 0219h near a number of other read-only registers. 006e rsvd gpio_dir[3:0] 006f rsvd gpi3sel[2] gpi2sel[2] gpi1sel[2] gpi0sel[2] 0070 rsvd gpi3sel[1] gpi2sel[1] gpi1sel[1] gpi0sel[1] 0071 rsvd gpi3sel[0] gpi2sel[0] gpi1sel[0] gpi0sel[0] 0072 rsvd gpo3sel[2] gpo2sel[2] gpo1sel[2] gpo0sel[2] 0073 rsvd gpo3sel[1] gpo2sel[1] gpo1sel[1] gpo0sel[1] 0074 rsvd gpo3sel[0] gpo2sel[0] gpo1sel[0] gpo0sel[0] 0075 rsvd 0076 rsvd gpo[3:0] gpio control register block field locations addre ss (hex) d7 d6 d5 d4 d3 d2 d1 d0 gpio control register block field descriptions bit field name field type default value description gpio_dir[3:0] r/w 00h direction control fo r general-purpose i/o pins gpio[3:0]: 0 = input mode 1 = output mode gpi0sel[2:0] r/w 000b function of gpio[0] pin when se t to in put mode by gpio_dir[0] r egister bit: 000 = general purpose input (valu e on gpio[0] pin directly refl ected in gpi[0] register bit) 001 = output enable control for output q0 010 = output enable control for output q4 011 = reserved 100 through 111 = reserved gpi1sel[2:0] r/w 000b function of gpio[1] pin when se t to in put mode by gpio_dir[1] r egister bit: 000 = general purpose input (valu e on gpio[1] pin directly refl ected in gpi[1] register bit) 001 = output enable control for output q1 010 = output enable control for output q5 011 through 111 = reserved gpi2sel[2:0] r/w 000b function of gpio[2] pin when se t to in put mode by gpio_dir[2] r egister bit: 000 = general purpose input (valu e on gpio[2] pin directly refl ected in gpi[2] register bit) 001 = output enable control for output q2 010 = output enable control for output q6 011 = reserved 100 = reserved 101 = csel0: manual clock select input for pll0 110 through 111 = reserved gpi3sel[2:0] r/w 000b function of gpio[3] pin when se t to in put mode by gpio_dir[3] r egister bit: 000 = general purpose input (valu e on gpio[3] pin directly refl ected in gpi[3] register bit) 001 = output enable control for output q3 010 = output enable control for output q7 011 = reserved 101 = csel1: manual clock select input for pll1 100, 110, 111 = reserved 28 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet gpo0sel[2:0] r/w 000b function of gpio[0] pin when set t o output mode by gpio_dir[0] register bit: 000 = general purpose output (va lue in gpo[0] regi ster bit driv en on gpio[0] pin 001 = loss-of-lock status flag f or digital pll0 reflected on gp io[0] pin 010 = loss-of-lock status flag f or digital pll1 reflected on gp io[0] pin 011 = reserved 100 = reserved 101 = reserved 110 through 111 = reserved gpo1sel[2:0] r/w 000b function of gpio[1] pin when set t o output mode by gpio_dir[1] register bit: 000 = general purpose output (va lue in gpo[1] regi ster bit driv en on gpio[1] pin 001 = holdover status flag for digital pll0 reflected on gpio[1 ] pin 010 = holdover status flag for digital pll1 reflected on gpio[1 ] pin 011 = reserved 100 = reserved 101 = reserved 110 = reserved 111 = reserved gpo2sel[2:0] r/w 000b function of gpio[2] pin when set t o output mode by gpio_dir[2] register bit: 000 = general purpose output (va lue in gpo[2] regi ster bit driv en on gpio[2] pin 001 = loss-of-signal flag for in put reference 0 reflected on gp io[2] pin 010 = loss-of-signal flag for in put reference 1 reflected on gp io[2] pin 011 = reserved 100 = reserved 101 through 111 = reserved gpo3sel[2:0] r/w 000b function of gpio[3] pin when set t o output mode by gpio_dir[3] register bit: 000 = general purpose output (va lue in gpo[3] regi ster bit driv en on gpio[3] pin 001 = loss-of-lock status flag f or digital pll1 reflected on gp io[3] pin 010 = loss-of-signal status flag for input reference 1 reflecte d on gpio[3] pin 011 = reserved 100 = reserved 101 through 111 = reserved gpo[3:0] r/w 00h output values reflect on pin gp io[3:0] when general-purpose out put mode selected. rsvd r/w - reserved. always write 0 to this b it location. read values are not defined. gpio control register block field descriptions bit field name field type default value description 29 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6j. output driver contro l register bit field locations a nd descriptions output driver control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0077 outen[7:0] 0078 pol_q[7:0] 0079 outmode7[2:0] se_mode7 outmode6[2:0] se_mode6 007a outmode5[2:0] se_mode 5 outmode4[2:0] se_mode4 007b outmode3[2:0] se_mode 3 outmode2[2:0] se_mode2 007c outmode1[2:0] se_mode1 outmode0[2:0] se_mode0 output driver control regist er block field descriptions bit field name field type default value description outen[7:0] r/w 00h output enable control for clo ck outputs q[7:0], nq[7:0]: 0 = qn is in a high-impedance state 1 = qn is enabled as i ndicated in appropria te outmode n[2:0] reg ister field pol_q[7:0] r/w 00h polarity of clock outputs q[7:0], nq[7:0]: 0 = normal polarity 1 = inverted polarity outmodem[2:0] r/w 001b output driver mode of operation for clock output pair qm, nqm: 000 = high-impedance 001 = lvpecl 010 = lvds 011 = lvcmos 100 = hcsl 101 - 111 = reserved se_modem r/w 0b behavior of output pai r qm, nqm when lvcmos operation is select ed: ? (must be 0 if lvds, hcsl or lvpec l output style is selected) 0 = qm and nqm are bot h the same frequency but inverted in phas e 1 = qm and nqm are both the same frequency and phase 30 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6k. output divider control register bit field locations a nd descriptions output divider control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 007d rsvd ns1_q0[1:0] 007e ns2_q0[15:8] 007f ns2_q0[7:0] 0080 rsvd ns1_q1[1:0] 0081 ns2_q1[15:8] 0082 ns2_q1[7:0] 0083 rsvd n_q2[17:16] 0084 n_q2[15:8] 0085 n_q2[7:0] 0086 rsvd n_q3[17:16] 0087 n_q3[15:8] 0088 n_q3[7:0] 0089 rsvd ns1_q4[1:0] 008a ns2_q4[15:8] 008b ns2_q4[7:0] 008c rsvd ns1_q5[1:0] 008d ns2_q5[15:8] 008e ns2_q5[7:0] 008f rsvd ns1_q6[1:0] 0090 ns2_q6[15:8] 0091 ns2_q6[7:0] 0092 rsvd ns1_q7[1:0] 0093 ns2_q7[15:8] 0094 ns2_q7[7:0] 0095 rsvd nfrac_q2[27:24] 0096 nfrac_q2[23:16] 0097 nfrac_q2[15:8] 0098 nfrac_q2[7:0] 0099 rsvd nfrac_q3[27:24] 009a nfrac_q3[23:16] 009b nfrac_q3[15:8] 009c nfrac_q3[7:0] 31 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet output divider control registe r block field descriptions bit field name field type default value description ns1_qm[1:0] (m = 0, 1) r/w 10b 1st stage output divider ratio fo r output clock qm, nqm: (m = 0 , 1): ? 00 = /5 01 = /6 10 = /4 11 = output qm, nqm not switching ns1_qm[1:0] (m = 4, 5, 6, 7) r/w 10b 1st stage output divider ratio fo r output clock qm, nqm (m = 4, 5, 6, 7): ? 00 = /5 01 = /6 10 = /4 11 = /1 (do not use this selection if pll0 or pll1 are the sour ce since the 2nd-stage divider has a limit of 1ghz.) ns2_qm[15:0] r/w 0002h 2nd stage output divider ratio fo r output clock qm, nqm (m = 0, 1, 4, 5, 6, 7): actual divider ratio is 2x the value written here. ? a value of 0 in this register will bypass the second stage of t he divider. n_qm[17:0] r/w 00008h integer portion of output divi der ratio for output clock qm, nq m (m = 2, 3): values of 0, 1 or 2 cannot be written to this register. ? actual divider ratio is 2x the value written here. nfrac_qm[27:0] r/w 0000000h fractional portion of output divider ratio for output clock qm, nqm (m = 2, 3): actual fractional portion is 2 x the value written here. ? fraction = (nfrac_qm * 2) * 2 -28 rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. 32 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6l. output clock phase adju stment control register bit fi eld locations and descriptions output clock phase adjustment con trol register block field loca tions address (hex) d7 d6 d5 d4 d3 d2 d1 d0 009d crse_trg[7:0] 009e rsvd coarse0[4:0] 009f rsvd coarse1[4:0] 00a0 rsvd coarse2[4:0] 00a1 rsvd coarse3[4:0] 00a2 rsvd coarse4[4:0] 00a3 rsvd coarse5[4:0] 00a4 rsvd coarse6[4:0] 00a5 rsvd coarse7[4:0] 00a6 rsvd fine2[3:0] 00a7 rsvd fine3[3:0] output clock phase adjustment c ontrol register b lock field desc riptions bit field name field type default value description crse_trg[7:0] r/w 00h trigger coarse phase adjustment fo r output qm, nqm by amount sp ecified in coarsem[4:0] register upon 0 ? 1 transition of this trigger re gister bit. plea se ensure the pa_busym status bit is 0 before triggering another adjustment c ycle on that particular output. trigger bit m ust be returned to 0 before another delay cycle can be triggered. coarsem[4:0] r/w 00000b number of periods to be insert ed when trigger happens. relevant clock period is determined by the clock source selected for output qm, nqm in i ts clk_selm register field. finem[3:0] r/w 0000b number of 1/16ths of the relevant clock period to add to the ph ase of output qm, nqm (m = 2,3). relevant clock period is determined by the clock source s elected for output qm, nqm in its clk_selm register field. the plln_syn bit for the pll dr iving the output divider for the output in question must be to ggled to make this value take effect. note that toggling the plln_syn bit will clear all coar se delay values and so fine del ay should be set first. rsvd r/w - reserved. alwa ys write 0 to this bi t location. read val ues are not defined. 33 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6m. output clock source c ontrol register bit field locati ons and descriptions output clock source control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 00a8 rsvd pll1_syn pll0_syn clk_sel3 clk_sel2 clk_sel1 clk_sel0 00a9 rsvd clk_sel5[2:0] rsvd clk_sel4[2:0] 00aa rsvd clk_sel7[2:0] rsvd clk_sel6[2:0] 00ab 11 11 rsvd rsvd output clock source control register block field descriptions bit field name field type default value description pll1_syn r/w 0b output synchronization control for outputs deri ved from pll1: setting this bit from 0 ? 1 will cause the output divider(s ) for the affected outputs to be held in reset. setting this bit from 1 ? 0 will release all the output div ider(s) for the affected outpu ts to run from the same point in time with the coarse output phase ad justment reset to 0. pll0_syn r/w 0b output synchronization control for outputs deri ved from pll0: setting this bit from 0 ? 1 will cause the output divider(s ) for the affected outputs to be held in reset. setting this bit from 1 ? 0 will release all the output div ider(s) for the affected outpu ts to run from the same point in time with the coarse output phase ad justment reset to 0. clk_sel0 r/w 0b clock source selection for output q0, nq0: 0 = pll0 1 = pll1 clk_sel1 r/w 1b clock source selection for output q1, nq1: 0 = pll0 1 = pll1 clk_sel2 r/w 0b clock source selection for output q2, nq2: 0 = pll0 1 = pll1 clk_sel3 r/w 1b clock source selection for output q3, nq3: 0 = pll0 1 = pll1 clk_sel4[2:0] r/w 000b clock source selection for output q4, nq4. do not select input reference 0 or 1 if that input is faster than 250mhz. 000 = pll0 001 = pll1 010 = output q2, nq2 011 = output q3, nq3 100 = input reference 0 (clk0) 101 = input reference 1 (clk1) 110 = reserved 111 = crystal input clk_sel5[2:0] r/w 010b clock source selection for output q5, nq5. do not select input reference 0 or 1 if that input is faster than 250mhz. 000 = pll0 001 = pll1 010 = output q2, nq2 011 = output q3, nq3 100 = input reference 0 (clk0) 101 = input reference 1 (clk1) 110 = reserved 111 = crystal input 34 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet clk_sel6[2:0] r/w 000b clock source selection for output q6, nq6. do not select input reference 0 or 1 if that input is faster than 250mhz. 000 = pll0 001 = pll1 010 = output q2, nq2 011 = output q3, nq3 100 = input reference 0 (clk0) 101 = input reference 1 (clk1) 110 = reserved 111 = crystal input clk_sel7[2:0] r/w 101b clock source selection for output q7, nq7. do not select input reference 0 or 1 if that input is faster than 250mhz. 000 = pll0 001 = pll1 010 = output q2, nq2 011 = output q3 nq3 100 = input reference 0 (clk0) 101 = input reference 1 (clk1) 110 = reserved 111 = crystal input rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. output clock source control register block field descriptions bit field name field type default value description 35 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 7 d e o h 1 $ q d o r j 3 / / & r q w u r o 5 h j l v w h u % l w ) l h o g / r f d w l r q v d q g ' h v f u l s w l r q v please contact idt through one o f the methods lis ted on the las t page of this datasheet for det ails on how to set these fields for a particular user configuration. 00ac cpset_0[2:0] rs_0[1:0] cp_0[1:0] wpost_0 00ad rsvd syn_mode 0 rsvd dlcnt_0 dbitm_0 00ae rsvd vcoman_0 dbit1_0[4:0] 00af rsvd dbit2_0[4:0] analog pll0 control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 analog pll0 control register block field descriptions bit field name field type default value description cpset_0[2:0] r/w 100b charge pump current setting for analog pll0: 000 = 110a 001 = 220a 010 = 330a 011 = 440a 100 = 550a 101 = 660a 110 = 770a 111 = 880a rs_0[1:0] r/w 01b internal loop filter series resi stor setti ng for analog pll0: 00 = 330 w 01 = 640 w 10 = 1.2k w 11 = 1.79k w cp_0[1:0] r/w 01b internal loop filter parallel c apa citor setting for analog pll0 : 00 = 40pf 01 = 80pf 10 = 140pf 11 = 200pf wpost_0 r/w 1b internal loop filter 2nd-pole setti ng for analog pll0: 0 = rpost = 497 w , c post = 40pf 1 = rpost = 1.58k w , cpost = 40pf dlcnt_0 r/w 1b digital lock count setting for analog pll0: value should be set to 0 (1ppm accu racy) if external capacitor value is >95nf, otherwise set to 1. 0 = 1ppm accuracy 1 = 16ppm accuracy dbitm_0 r/w 0b digital lock manual overri de setti ng for analog pll0: 0 = automatic mode 1 = manual mode vcoman_0 r/w 1b manual lock mode vco selection setting for analog pll0: 0 = vco2 1 = vco1 dbit1_0[4:0] r/w 01011b manual mode digital lock control se tting for vco1 in analog pll 0. 36 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 7 d e o h 2 $ q d o r j 3 / / & r q w u r o 5 h j l v w h u % l w ) l h o g / r f d w l r q v d q g ' h v f u l s w l r q v please contact idt through one o f the methods lis ted on the las t page of this datasheet for det ails on how to set these fields for a particular user configuration. 00b0 cpset_1[2:0] rs_1[1:0] cp_1[1:0] wpost_1 00b1 rsvd syn_mod e1 rsvd dlcnt_1 dbitm_1 00b2 rsvd vcoman_1 dbit1_1[4:0] 00b3 rsvd dbit2_1[4:0] dbit2_0[4:0] r/w 00000b manual mode digital lock control se tting for vco2 in analog pll 0. syn_mode0 r/w 0b frequency synthesizer mode control for pll0: 0 = pll0 jitter attenuates and tr an slates one or more input ref erences 1 = pll0 synthesizes output fre que ncies using only the crystal as a reference note that the state0[1:0] field in the digital pll0 control reg iste r must be set to force freerun state. rsvd r/w - reserved. always write 0 to this b it l ocation. read values are not defined. analog pll1 control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 analog pll1 control register block field descriptions bit field name field type default value description cpset_1[2:0] r/w 100b charge pump current setting for analog pll1: 000 = 110a 001 = 220a 010 = 330a 011 = 440a 100 = 550a 101 = 660a 110 = 770a 111 = 880a rs_1[1:0] r/w 01b internal loop filter series re sistor se tting for analog pll1: 00 = 330 w 01 = 640 w 10 = 1.2k w 11 = 1.79k w cp_1[1:0] r/w 01b internal loop filter parallel capacitor setting for analog pll1 : 00 = 40pf 01 = 80pf 10 = 140pf 11 = 200pf wpost_1 r/w 1b internal loop filter 2nd-po l e setting for analog pll1: 0 = rpost = 497 w , cp ost = 40pf 1 = rpost = 1.58k w , cpost = 40pf dlcnt_1 r/w 1b digital lock count setting for analog pll1: value should be set t o 0 (1ppm accuracy) if e xternal capacitor value is >95nf, otherwise set to 1. 0 = 1ppm accuracy 1 = 16ppm accuracy dbitm_1 r/w 0b digital lock manual override se tting for analog pll1: 0 = automatic mode 1 = manual mode analog pll0 control register block field descriptions bit field name field type default value description 37 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6p. power down control reg ister bit field locations and d escriptions vcoman_1 r/w 1b manual lock mode vco select ion setting for analog pll1: 0 = vco2 1 = vco1 dbit1_1[4:0] r/w 01011b manual mode digital lock control setting for vco1 in analog pll 1. dbit2_1[4:0] r/w 00000b manual mode digital lock control setting for vco2 in analog pll 1. syn_mode1 r/w 0b frequency synthesizer m ode control for pll1: 0 = pll1 jitter attenua tes and translates one or more input ref erences 1 = pll1 synthesizes output freq uencies using only the crystal as a reference note that the state1[ 1:0] field in the dig ital pll1 control reg ister must be set to force freerun state. rsvd r/w - reserved. always write 0 to thi s bit location. read values are not defined. power down control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 00b4 rsvd dbl_dis 00b5 rsvd 1 1 clk1_dis clk0_dis 00b6 rsvd pll1_dis rsvd 00b7 q7_dis q6_dis q5_dis q4_dis q3_dis q2_dis q1_dis q0_dis 00b8 rsvd dpll1_dis dpll0_dis calrst1 calrst0 power down control register block field descriptions bit field name field type default value description dbl_dis r/w 0b controls whether crystal input f requency is doubled before bein g used in pll0 or pll1: 0 = 2x actual crystal frequency used 1 = actual crystal frequency used clkm_dis r/w 0b disable control for input reference m: 0 = input reference m is enabled 1 = input reference m is disabled pll1_dis r/w 0b disable control for analog pll1: 0 = pll1 enabled 1 = analog pll1 disabled qm_dis r/w 0b disable control for output qm, nqm: 0 = output qm, nqm functions normally 1 = all logic associated with ou tput qm, nqm is disabled & driv er in high-impedance state dpllm_dis r/w 0b disable control for digital pllm: 0 = digital pllm enabled 1 = digital pllm disabled calrstm r/w 0b reset calibration logic for apllm: 0 = calibration logic for apllm enabled 1 = calibration logic for apllm disabled rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. analog pll1 control register block field descriptions bit field name field type default value description 38 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6q. input monitor control register bit fie ld locations an d descriptions table 6r. interrupt enable contro l register bit field locations and descriptions input monitor control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 00b9 rsvd los_0[16] 00ba los_0[15:8] 00bb los_0[7:0] 00bc rsvd los_1[16] 00bd los_1[15:8] 00be los_1[7:0] 00bf rsvd rsvd 00c0 rsvd 00c1 rsvd 00c2 rsvd rsvd 00c3 rsvd 00c4 rsvd 00c5 rsvd 00c6 rsvd input monitor control register block field descriptions bit field name field type default value description los_m[16:0] r/w 1ffffh number of input monitoring clock periods before input reference m is considered to be missed (soft alarm). m inimum setting is 3. rsvd r/w - reserved. al ways write 0 to this bit location. read val ues are not defined. interrupt enable control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 00c7 lol1_en lol0_en hold1_en hold0_en rsvd rsvd los1_en los0_en interrupt enable control register block field descriptions bit field name field type default value description lolm_en r/w 0b interrupt enable control for loss- of-lock interrupt status bit for pllm: 0 = lolm_int register bit will not affect status of nint output signal 1 = lolm_int register bit will af fect status of nint output sig nal holdm_en r/w 0b interrupt enable control for hold over interrupt status bit for pllm: 0 = holdm_int register bit wi ll not affect status of nint outpu t signal 1 = holdm_int register bit will affect status of nint output si gnal losm_en r/w 0b interrupt enable control for loss- of-signal interrupt status bi t for input reference m: 0 = losm_int register bit will no t affect status of nint output signal 1 = losm_int register bit will affect status of nint output sig nal 39 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 7 d e o h 6 ' l j l w d o 3 k d v h ' h w h f w r u & r q w u r o 5 h j l v w h u % l w ) l h o g / r f d w l r q v d q g ' h v f u l s w l r q v 7 d e o h 7 , q w h u u x s w 6 w d w x v 5 h j l v w h u % l w ) l h o g / r f d w l r q v d q g ' h v f u l s w l r q v this register contains sticky b its for tracking the status of the various alarms. whenever an alarm occurs, the appropriate interrupt status bit will be set. the interrupt status bit will remain asserted even after the original alarm goes away. the interrupt status bits remain asserted until explicitly cleared by a write of a 1 to the bit over the seri al port. this type of functionalit y is referred to as read / wr ite-1-to-clear (r/w1c). 0200 lol1_int lol0_int hold1_int hold0_int rsvd rsvd los1_int los0_int 0201 rsvd 0202 rsvd 0203 rsvd lolm_int r/w1c 0b interrupt status bit fo r l oss-of-lock on pllm: 0 = no loss-of-lock al arm flag on pllm has occurred since the l ast time this register bit was cleared 1 = at least one loss-of-lock alarm flag on pllm has occurred s i nce the last time this register bit was cleared holdm_int r/w1c 0b interrupt status bit for holdover on pllm: 0 = no holdover alarm flag on pllm h as occurred since the last time this register bit was cleared 1 = at least one holdover alarm fl ag on pllm has occurred since the last time this register bit was cleared losm_int r/w1c 0b interrupt status bit for loss-of -si gnal on input reference m: 0 = no loss-of-signal alarm flag on input reference m has occurred since the last time this register bit was cleared 1 = at least one loss-of-signal alarm flag on input reference m has occurred since the last time this register bit was cleared rsvd r/w - reserved. always write 0 to thi s bi t location. read values are not defined. digital phase detector control register block field locations a d d r e s s ( h e x )d 7d 6d 5d 4d 3d 2d 1d 0 00c8 27h 00c9 rsvd 1 rsvd 1 rsvd rsvd 00ca 27h 00cb rsvd 1 rsvd 1 rsvd rsvd digital phase detector control register block field description s bit field name field type default value description rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 interrupt status register block field descriptions bit field name field type default value description 40 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6u. output phase adjustment status register bit field loc ations and descriptions the following register is included for debug purposes only. it shows the actual digital pll0 st ate directly. this means that t he bits may change rapidly as the dpll operates. the fields in this register do no t represent a snapshot in time , so they may be inconsistent w ith one another if the dpll is rapidly changing at the time of reading. fast chang es in the status of the pll can not be captured b y polling these bits, in which case, idt recommends using the s ticky bits interrupts and gpios . table 6v. digital pll0 status re gister bit field locations and descriptions output phase adjustment status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0204 pa_busy7 pa_busy6 pa_busy5 pa_busy4 pa_busy3 pa_busy2 pa_busy1 pa_ busy0 output phase adjustment status register block field descriptions bit field name field type default value description pa_busym r/o - phase adjustment event s tatus for output qm, nqm: 0 = no phase adjustme nt is currently in pr ogress on output qm, nqm 1 = phase adjustment still in pro gress on output qm, nqm. do no t initiate any new phase adjustment at this time digital pll0 status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0205 rsvd extlos0 no_ref0 curr_ref0[2:0] 0206 rsvd pll0lck rsvd rsvd sm_sts0[1:0] 0207 rsvd rsvd 0208 rsvd 0209 rsvd 020a rsvd rsvd 020b rsvd 020c rsvd 020d rsvd 020e rsvd digital pll0 status register block field descriptions bit field name field type default value description extlos0 r/o - external loopback signal lost for pll0: 0 = pll0 has a valid f eedback reference signal 1 = pll0 has lost the external feedback reference signal and is no longer locked no_ref0 r/o - valid reference stat us for digital pll0: 0 = at least one valid i nput reference is present 1 = no valid input references present curr_ref0[2:0] r/o - currently selected referenc e status for digital pll0: 000 - 011 = no referenc e currently selected 100 = input reference 0 (clk0, nclk0) selected 101 = input reference 1 (clk1, nclk1) selected 110 = reserved 111 = reserved 41 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet the following register is included for debug purposes only. it shows the actual digital pll1 st ate directly. this means that t he bits may change rapidly as the dpll operates. the fields in this register do no t represent a snapshot in time , so they may be inconsistent w ith one another if the dpll is rapidly changing at the time of read ing. fast chang es in the status of the pll can not be captured b y polling these bits, in which case, idt recommends u sing the sticky bits interrupts and gpios . table 6w. digital pll1 status re gister bit field locations and descriptions pll0lck r/o - digital pll0 phase error value is less than lock criteria. not asserted if pll0 in synthesizer mode. sm_sts0[1:0] r/o - current state of digital pll0: 00 = reserved 01 = freerun 10 = normal 11 = holdover rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. digital pll0 status register block field descriptions bit field name field type default value description digital pll1 status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 020f rsvd extlos1 no_ref1 curr_ref1[2:0] 0210 rsvd pll1lck rsvd rsvd sm_sts1[1:0] 0211 rsvd rsvd 0212 rsvd 0213 rsvd 0214 rsvd rsvd 0215 rsvd 0216 rsvd 0217 rsvd 0218 rsvd digital pll1 status register block field descriptions bit field name field type default va lue description extlos1 r/o - external loopback signal lost for pll1: 0 = pll1 has a valid feedback reference signal 1 = pll1 has lost the external feedback reference signal and is no longer locked no_ref1 r/o - valid reference stat us for digital pll1: 0 = at least one valid in put reference is present 1 = no valid input references present curr_ref1[2:0] r/o - currently selected referenc e status for digital pll1: 000 - 011 = no referen ce currently selected 100 = input reference 0 (clk0, nclk0) selected 101 = input reference 1 (clk1, nclk1) selected 110 = reserved 111 = reserved 42 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 6x. general purpose input status register bit field locat ions and descriptions table 6y. global interrupt statu s register bit f ield locations and descriptions pll1lck r/o - digital pll1 phase error value is less than the lock window setting . not asserted if pll1 in synthesizer mode. sm_sts1[1:0] r/o - current state of digital pll1: 00 = reserved 01 = freerun 10 = normal 11 = holdover rsvd r/w - reserved. alwa ys write 0 to this bit location. read val ues are not defined. digital pll1 status register block field descriptions bit field name field type default va lue description global interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0219 rsvd gpi[3] gpi[2] gpi[1] gpi[0] general purpose input status register block field descriptions bit field name field type default value description gpi[3:0] r/o - shows current values on gpio[3:0] pins that are configured as g eneral-purpose inputs. global interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 021a rsvd rsvd int 021b rsvd 021c rsvd cali_dbit0[5:0] 021d rsvd cali_dbit1[5:0] 021e rsvd rsvd rsvd bootfail 021f rsvd rsvd rsvd rsvd neep_crc rsvd rsvd eepdone global interrupt status register block field descriptions bit field name field type default value description int r/o - device interrupt status: 0 = no interrupt status bits tha t are enabled are asserted (nin t pin released) 1 = at least one inte rrupt status bit tha t is enabled is assert ed (nint pin asserted low) bootfail r/o - reading of serial eeprom failed. onc e set thi s bit is only cleared by reset. neep_crc r/o - eeprom crc error (active low): 0 = eeprom was detect ed and read, but crc check failed - please reset the device via the nrst pin to retry (serial port is locked) 1 = no eeprom crc error eepdone r/o - serial eeprom read cycle has completed. once set thi s bit is only cleared by reset. cali_dbitn[5:0] r/o - indicates cu rrent digital bit setting for pl ln. rsvd r/w - reserved. always write 0 to this bit location. read val ues are not defined. 43 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet $ e v r o x w h 0 d [ l p x p 5 d w l q j v note: stresses beyond those listed under may cause permanent damage to the device. these ratings are st ress specifications only. functional operation of product at these c onditions or any conditions beyond those listed in the is not implied. exposure to abs olute maximum rating conditions for extended periods may affect product reliability. supply voltage, v cc 3.63v inputs, v i osci other input 0v to 2v -0.5v to v cc + 0.5v outputs, v o (q[0:7], nq[0:7]) -0.5v to v ccox + 0.5v outputs, v o (gpio[0:3], sdata, sclk, nint) -0.5v to v cc + 0.5v outputs, i o (q[0:7], nq[0:7]) continuous current surge current 40ma 65ma outputs, i o (gpio[0:3], sdata, sclk, nint) continuous current surge current 8ma 13ma junction temperature, t j 125c storage temperature, t stg -65 c to 150 c note: v ccox denotes v cco0, v cco1, v cco2, v cco3, v cco4, v cco5, v cco6, v cco7. supply voltage characteristics table 7a. power suppl y characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1: i cc and i cca are included in i ee when q[0:7] con figured for lvpecl logic levels. note 2: internal dynamic s witching current at maximum f out is included. item rating symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc C 0.13 3.3 v cc v i cc core supply current; note 1 74 100 ma i cca analog supply current; note 1 pll0 and pll1 enabled 206 265 ma analog pll1, digital pll1, and calibration logic for analog pll1 disabled 122 187 ma i ee power supply current; note 2 q[0:7] configured for lvpecl logic levels, outputs unloaded 562 735 ma 44 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 7b. power suppl y characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: i cc and i cca are included in i ee when q[0:7] con figured for lvpecl logic levels. ? note 2: internal dynamic s witching current at maximum f out is included. table 7c. maximum output supply current, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: internal dynamic switching current at maximum f out is included. ? note: v ccox denotes v cco0, v cco1, v cco2, v cco3, v cco4, v cco5, v cco6, v cco7. symbol parameter test conditions minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage v cc C 0.13 2.5 v cc v i cc core supply current; ? note 1 72 95 ma i cca analog supply current; note 1 pll0 and pll1 enabled 201 260 ma analog pll1, digital pll1, and calibration logic for analog pll1 disabled 119 182 ma i ee power supply current; ? note 2 q[0:7] configured for lvpecl logic levels, outputs unloaded 533 695 ma symbol parameter test conditions v ccox = 3.3v 5% v ccox = 2.5v 5% v ccox = 1.8v 5% units lvpecl lvds hcsl lvcmos lvpecl lvds hcsl lvcmos lvcmos i cco0 q0, nq0 output ? supply current outputs unloaded 50 60 50 55 40 50 40 45 35 ma i cco1 q1, nq1 output ? supply current outputs unloaded 50 60 50 55 40 50 40 45 35 ma i cco2 q2, nq2 output ? supply current outputs unloaded 80 90 80 80 70 80 70 70 60 ma i cco3 q3, nq3 output ? supply current outputs unloaded 80 90 80 80 70 80 70 70 60 ma i cco4 q4, nq4 output ? supply current outputs unloaded 55 65 55 55 45 55 45 45 40 ma i cco5 q5, nq5 output ? supply current outputs unloaded 55 65 55 55 45 55 45 45 40 ma i cco6 q6, nq6 output ? supply current outputs unloaded 55 65 55 55 45 55 45 45 40 ma i cco7 q7, nq7 output ? supply current outputs unloaded 55 65 55 55 45 55 45 45 40 ma 45 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet dc electrical characteristics table 8a. lvcmos/lvttl dc characteristics, v ee = 0v, t a = -40c to 85c note 1: use of external pull- up resistors is recommended. table 8b. differential i nput dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: clkx denotes clk0, clk1 . nclkx denotes nclk0, nclk1. ? note 1: v il should not be less than -0.3v. v ih should not be higher than v cc. ? note 2: common mode voltage i s defined as the cross-point. symbol parameter test conditions minimum typical maximum units v ih input high voltage v cc = 3.3v 2 v cc +0.3 v v cc = 2.5v 1.7 v cc +0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input ? high current pll_byp, s_a0 v cc = v in = 3.465v or 2.625v 150 a nrst, sdata, sclk v cc = v in = 3.465v or 2.625v 5 a gpio[3:0] v cc = v in = 3.465v or 2.625v 1 ma i il input ? low current pll_byp, s_a0 v cc = 3.465v or 2.625v, v in = 0v -5 a nrst, sdata, sclk v cc = 3.465v or 2.625v, v in = 0v -150 a gpio[3:0] v cc = 3.465v or 2.625v, v in = 0v -1 ma v oh output ? high voltage nint, sdata, ? sclk; note 1 v cc = 3.3v 5%, i oh = -5a 2.6 v gpio[3:0] v cc = 3.3v 5%, i oh = -50a 2.6 v nint, sdata, ? sclk; note 1 v cc = 2.5v 5%, i oh = -5a 1.8 v gpio[3:0] v cc = 2.5v 5%, i oh = -50a 1.8 v v ol output ? low voltage nint, sdata, ? sclk; note 1 v cc = 3.3v 5% or 2.5v5%, i ol = 5ma 0.5 v gpio[3:0] v cc = 3.3v 5% or 2.5v5%, i ol = 5ma 0.5 v symbol parameter test conditio ns minimum typical maximum units i ih input high current clkx, nclkx v cc = v in = 3.465v or 2.625v 150 a i il input low current clkx v cc = 3.465v or 2.625v, v in = 0v -5 a nclkx v cc = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee v cc -1.2 v 46 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 8c. lvpecl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: v ccox denotes v cco0, v cco1, v cco2, v cco3, v cco4, v cco5, v cco6, v cco7. ? note: qx denotes q0, q1 , q2, q3, q4, q5, q6 , q7. nqx denotes nq 0, nq1, nq2, nq3, nq4, nq5, nq6, nq7. ? note 1: outputs terminated with 50 ? to v ccox C 2v. table 8d. lvds dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5% or 2.5v 5%, v ee = 0v, ? t a = -40c to 85c note: v ccox denotes v cco0, v cco1, v cco2, v cco3, v cco4, v cco5, v cco6, v cco7. ? note: qx denotes q0, q1 , q2, q3, q4, q5, q6 , q7. nqx denotes nq 0, nq1, nq2, nq3, nq4, nq5, nq6, nq7. ? note: terminated 100 ? across qx and nqx. table 8e. lvcmos dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: qx denotes q0, q1 , q2, q3, q4, q5, q6 , q7. nqx denotes nq 0, nq1, nq2, nq3, nq4, nq5, nq6, nq7. ? note: v ccox denotes v cco0, v cco1, v cco2, v cco3, v cco4, v cco5, v cco6, v cco7. symbol parameter test conditions v ccox = 3.3v5% v ccox = 2.5v5% units minimum typical maximum minimum typical maximum v oh output ? high voltage; ? note 1 qx, ? nqx v ccox - 1.3 v ccox - 0.8 v ccox - 1.4 v ccox - 0.9 v v ol output ? low voltage; ? note 1 qx, ? nqx v ccox - 1.95 v ccox - 1.75 v ccox - 1.95 v ccox - 1.75 v symbol parameter test conditions minimum typical maximum units v od differential output voltage qx, nqx 195 454 mv ? v od v od magnitude change qx, nqx 50 mv v os offset voltage qx, nqx 1.1 1.375 v ? v os v os magnitude change qx, nqx 50 mv symbol parameter test conditions v ccox = 3.3v5% v ccox = 2.5v5% v ccox = 1.8v 5% units minimum typical maximum minimum typical maximum minimum typical maximum v oh output ? high voltage qx, ? nqx i oh = -8ma 2.6 1.8 1.1 v v ol output ? low voltage qx, ? nqx i ol = 8ma 0.5 0.5 0.5 v 47 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 9. input frequency characteristics, v cc = 3.3v5% or 2.5v5%, t a = -40c to 85c note: clkx denotes clk0, clk1 . nclkx denotes nclk0, nclk1. ? note 1: for the input reference frequency, the divider values m ust be set for the vc o to operate within it s supported range. ? note 2. for optimal noise perform ance, the use of a quartz crys tal is recommended. refer to applications information, overdriving the crystal interface . table 10. crystal characteristics symbol parameter test conditio ns minimum typical maximum units f in input frequency; note 1 osci, osco using a crystal (see table 10 , crystal characteristics) 10 40 mhz overdriving crystal input, doubler logic enabled; note 2 10 62.5 mhz overdriving crystal input, doubler logic disabled; note 2 16 125 mhz clkx, nclkx 0.008 875 mhz f sclk serial port clock sclk slave mode 100 400 khz parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 10 40 mhz equivalent series resistance (esr) 15 ? load capacitance (c l ) 12 pf frequency stability (total) -100 100 ppm 48 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet ac electrical characteristics table 11a. ac ch aracteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only supported for lvcmos outputs), t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units f vco vco operating frequency 3000 4000 mhz f out output frequency lvpecl, lvds, hcsl q0, q1, q4 , q5, q6, q7 outputs 0.008 1000 mhz q2, q3 outputs integer divide ratio & no added phase delay 0.008 666.67 mhz q2, q3 outputs non-integer divide and/or added phase delay 0.008 400 mhz lvcmos 0.008 250 mhz t r / t f output ? rise and fall times lvpecl 20% to 80% 145 360 600 ps lvds 20% to 80% 100 230 400 ps hcsl 20% to 80% 150 300 600 ps lvcmos; note 1, 2 20% to 80%, v ccox = 3.3v 180 350 600 ps 20% to 80%, v ccox = 2.5v 200 350 550 ps 20% to 80%, v ccox = 1.8v 200 410 650 ps sr output ? slew rate; ? note 3 lvpecl measured on differential waveform, 150mv from center 15v/ns lvds measured on differential waveform, 150mv from center 0.5 4 v/ns hcsl v ccox = 2.5v, f out ? 125mhz; measured on differential waveform, 150mv from center 1.5 4 v/ns v ccox = 3.3v, f out ? 125mhz; measured on differential waveform, 150mv from center 2.5 5.5 v/ns 49 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet t sk(b) bank skew lvpecl q0, nq0, q1, nq1 note 4, 5, 6, 7 75 ps q4, nq4, q5, nq5 note 4, 5, 6, 7 75 ps q6, nq6, q7, nq7 note 4, 5, 6, 7 75 ps lvds q0, nq0, q1, nq1 note 4, 5, 6, 7 75 ps q4, nq4, q5, nq5 note 4, 5, 6, 7 75 ps q6, nq6, q7,nq7 note 4, 5, 6, 7 75 ps hcsl q0, nq0, q1, nq1 note 4, 5, 6, 7 75 ps q4, nq4, q5, nq5 note 4, 5, 6, 7 75 ps q6, nq6, q7, nq7 note 4, 5, 6, 7 75 ps lvcmos q0, nq0, q1, nq1 note 1, 4, 5, 7, 8 80 ps q4, nq4, q5, nq5 note 1, 4, 5, 7, 8 115 ps q6, nq6, q7, nq7 note 1, 4, 5, 7, 8 115 ps odc output ? duty cycle; ? note 9 lvpecl, lvds, hcsl f out ? 666.667mhz 45 50 55 % f out > 666.667mhz 40 50 60 % lvcmos 40 50 60 % initial frequency offset; ? note 10, 11, 12 switchover or entering / leaving holdover state -50 50 ppb output phase change in fully hitless switching; note 11, 12, 13 switchover or entering / leaving holdover state 5ns ? ssb (1k) single sideband ? phase noise; ? note 14 1khz 122.88mhz output -123 dbc/hz ? ssb (10k) 10khz 122.88mhz output -131 dbc/hz ? ssb (100k) 100khz 122.88mhz output -134 dbc/hz ? ssb (1m) 1mhz 122.88mhz output -147 dbc/hz ? ssb (10m) 10mhz 122.88mhz output -153 dbc/hz ? ssb (30m) ? 30mhz 122.88mhz output -154 dbc/hz spurious limit at offset; note 15 ? 800khz 122.88mhz output -83 dbc symbol parameter test conditio ns minimum typical maximum units 50 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet note: v ccox denotes v cco0, v cco1, v cco2, v cco3, v cco4, v cco5, v cco6, v cco7. ? note: electrical parameters ar e guaranteed over t he specified a mbient operating temperature ra nge, which is established when t he device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the devic e will meet specifications afte r thermal equilibrium has been reached under these conditions. ? note 1: appropriate se_mode bit m ust be configured to select ph ase-aligned or phase-inverted operation. ? note 2: all q and nq outputs in phase-inverted operation ? note 3: measured from -150mv to + 150mv on the differential wave form (derived from qx minus nqx). the signal must be monotonic through the measurement region fo r rise and fall time. the 300m v measurement window is centered on the differential zero cross ing. ? note 4: this parameter is guarant eed by characterization. not t ested in production. ? note 5: this parameter is defined in accordance with jedec stan dard 65. ? note 6: measured at the outpu t differential cross point. ? note 7: defined as skew within a bank of outputs at the same su pply voltage and with equal load conditi ons running off the sam e pll. ? note 8: measured at v ccox /2 of the rising edge. all qx a nd nqx outputs phase-aligned. ? note 9: characterized in synthesizer mo de. duty cycle of bypassed signa ls (input reference clocks or crystal input) is not adjusted by the device. ? note 10: tested in fast-lock ope ration after >20 minutes of loc ked operation to ens ure holdover averaging logic is stable. ? note 11: this parameter is guaranteed by design. ? note 12: using internal feedback mode configuration. ? note 13: device programmed with swmoden = 0 (absorbs phase diff erences). ? note 14: characterized with 8t4 9n287b-901 units (synthesizer mo de). ? note 15: tested with all outputs operat ing at 122.88mhz. ? note 16: assuming a clear i 2 c bus. ? note 17: this parameter was measured usi ng clk0 as the reference input a nd clk1 as the external feedback input. characterized with 8t49n287-908. ? ? t startup startup time internal ? otp startup; ? note 11 from v cc >80% to first output clock edge 110 150 ms external ? eeprom startup; ? note 11, 16 from v cc >80% to first output clock edge (0 retries); i 2 c frequency = 100khz 150 200 ms from v cc >80% to first output clock edge (0 retries); i 2 c frequency = 400khz 130 150 ms from v cc >80% to first output clock edge (31 retries); i 2 c frequency = 100khz 925 1200 ms from v cc >80% to first output clock edge (31 retries); i 2 c frequency = 400khz 360 500 ms ? spo static phase offset variation; note 17 f in = f out = 156.25mhz -175 175 ps symbol parameter test conditio ns minimum typical maximum units 51 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 11b. hcsl ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5% or 2.5v 5%, t a = -40c to 85c note: electrical parameters ar e guaranteed over t he specified a mbient operating temperature ra nge, which is established when t he device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the devic e will meet specifications afte r thermal equilibrium has been reached under these conditions. note 1: measurement taken f rom differential waveform. note 2: t stable is the time the differential cl ock must maintai n a minimum 15 0mv differential voltage after rising/falling edg es before it i s allowed to drop back into the v rb 100mv differential range. note 3: measurement taken from single ended waveform. note 4: defined as the maximum instantaneous voltage including overshoot. ? note 5: defined as the minimum i nstantaneous voltage including undershoot. ? note 6: measured at crossing poi nt where the instantaneous volt age value of the risi ng edge of qn equ als the falling edge of n qn. note 7: refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. ref ers to all crossing points for this measurement. note 8: defined as the total vari ation of all crossing voltages of rising qn and falling nqn. t his is the maximum allowed vari ance in v cross for any partic ular system. symbol parameter test conditi ons minimum typical maximum units v rb ring-back voltage margin; ? note 1, 2 -100 100 mv t stable time before v rb is allowed; ? note 1, 2 500 ps v max absolute max. output voltage; note 3, 4 1150 mv v min absolute min. output voltage; note 3, 5 -300 mv v cross absolute crossing voltage; ? note 6, 7 230 550 mv ? v cross total variation of v cross over all edges; note 6, 8 140 mv 52 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 12a. typical rms phase jitter (synthesizer mode), v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or ? 1.8v 5% (1.8v only supported for lvcmos outputs), t a = -40c to 85c note: v ccox denotes v cco0, v cco1, v cco2, v cco3, v cco4, v cco5, v cco6, v cco7. ? note: fox part numbers: 277lf-40- 18 and 277lf-38.88-2 used for 40mhz and 38.88mhz cry stals, respectively. ? note: all outputs configured for the specific output type, as s hown in the table. ? note 1: characteri zed with 8t49n287-901. ? note 2: characteri zed with 8t49n287-902. ? note 3: characteri zed with 8t49n287-903. ? note 4: characteri zed with 8t49n287-900. ? note 5: this frequency is not s upported for lvcmos operation. ? note 6: qx and nqx are 180 out of phase. table 12b. typical rms phase jitter (jitter attenuator mode), v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only suppor ted for lvcmos outputs), t a = -40c to 85c note: v ccox denotes v cco0, v cco1, v cco2, v cco3, v cco4, v cco5, v cco6, v cco7. ? note: measured using a rohde & s chwarz sma100a as the input sou rce. ? note: fox part numbers: 277lf-40- 18 and 277lf-38.88-2 used for 40mhz and 38.88mhz cry stals, respectively. ? note: all outputs configured for the specific output type, as s hown in the table. ? note 1: characteri zed with 8t49n287-905. ? note 2: characteri zed with 8t49n287-906. ? note 3: characteri zed with 8t49n287-907. ? note 4: characteri zed with 8t49n287-904. ? note 5: this frequency is not s upported for lvcmos operation. ? note 6: qx and nqx are 180 out of phase. symbol parameter test co nditions lvpecl lvds hcsl lvcmos note 6 units tjit( ? ) rms phase jitter (random) q0, q1 f out = 122.88mhz, integration range: 12khz - 20mhz; note 1 282 299 280 287 fs f out = 156.25mhz, integration range: 12khz - 20mhz; note 2 265 264 263 270 fs f out = 622.08mhz, integration range: 12khz - 20mhz; note 3 289 266 265 n/a ( note 5 ) fs q2, q3 integer; ? note 1 f out = 122.88mhz, integration range: 12khz - 20mhz 312 326 304 318 fs q2, q3 fractional; ? note 4 f out = 122.88mhz, integration range: 12khz - 20mhz 269 280 261 263 fs q4, q5, q6, q7; ? note 1 f out = 122.88mhz, integration range: 12khz - 20mhz 302 321 295 301 fs symbol parameter test co nditions lvpecl lvds hcsl lvcmos note 6 units tjit( ? ) rms phase jitter (random) q0, q1 f out = 122.88mhz, integration range: 12khz - 20mhz; note 1 285 299 280 275 fs f out = 156.25mhz, integration range: 12khz - 20mhz; note 2 261 252 264 274 fs f out = 622.08mhz, integration range: 12khz - 20mhz; note 3 221 203 202 n/a ( note 5 ) fs q2, q3 integer; ? note 1 f out = 122.88mhz, integration range : 12khz - 20mhz 312 327 306 306 fs q2, q3 fractional; ? note 4 f out = 122.88mhz, integration range : 12khz - 20mhz 271 282 263 267 fs q4, q5, q6, q7; ? note 1 f out = 122.88mhz, integration range : 12khz - 20mhz 308 320 295 288 fs 53 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 13. pci express j itter specifications, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5% or 2.5v 5%, ? t a = -40c to 85c note: v ccox denotes v cco0, v cco1, v cco2, v cco3, v cco4, v cco5, v cco6, v cco7. ? note: electrical parameters ar e guaranteed over t he specified a mbient operating temperature ra nge, which is established when t he device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the devic e will meet specifications afte r thermal equilibrium has been reached under these conditions. ? note 1: peak-to-peak jitter a fter applying system transfer func tion for the common clock architec ture. maximum limit for pci e xpress gen 1 ? note 2: rms jitter after applying the two evaluation bands to t he two transfer funct ions defined in the common clock architect ure and reporting the worst case results for each evaluation band. maxi mum limit for pci express gene ration 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3. 0ps rms for t refclk_lf_rms (low band). ? note 3: rms jitter after apply ing system transfer function for the common clock architecture. this specification is based on t he pci express base specification revision 0.7 , october 2009 and is subject to change pending the final release version of the specification. ? note 4: this parameter is guarant eed by characterization. not t ested in production. ? note 5: outputs configured for hcsl mode. fox 277lf-40-18 cryst al used with doubl er logic enabled. symbol parameter test conditions minimum typical maximum pcie industry specification units tj (pcie gen 1) phase jitter peak-to-peak; ? note 1, 4, 5 ? = 100mhz, 40mhz crystal input, evaluation band: 0hz - nyquist (clock frequency/2) 816 86 ps t refclk_hf_rms (pcie gen 2) phase jitter rms; ? note 2, 4, 5 ? = 100mhz, 40mhz crystal input, high band: 1.5mhz - nyquist (clock frequency/2) 0.8 1.8 3.1 ps t refclk_lf_rms (pcie gen 2) phase jitter rms; ? note 2, 4, 5 ? = 100mhz, 40mhz crystal input, low band: 10khz - 1.5mhz 0.03 0.5 3.0 ps t refclk_rms (pcie gen 3) phase jitter rms; ? note 3, 4, 5 ? = 100mhz, 40mhz crystal input, evaluation band: 0hz - nyquist (clock frequency/2) 0.2 0.5 0.8 ps 54 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet typical phase noise at 156.25mhz ? noise power dbc/hz offset frequency (hz) 55 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet applications information overdriving the crystal interface the osci input can be ov erdriven by an lvcmos driver or by one side of a differential driver t hrough an ac coupling capacitor. the osco pin can be left floating. t he amplitude of the input signa l should be between 500mv and 1.8v and the slew rate should not b e less than 0.2v/ns. for 3.3v lvcm os inputs, the amplitude must b e reduced from full swing to at l east half the swing in order to prevent signal interference with the powe r rail and to r educe internal noise. figure 5a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of the driver (ro) and the series resis tance (rs) equals the transmission l ine impedance. in addition, match ed termination at the crystal inpu t will attenuate the signal in h alf. this can be done in one of t wo ways. first, r1 and r2 in parallel sh ould equal the transmission li ne impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading f or a slower and weaker lvcmos driver. figure 5b shows an exampl e of the interfac e diagram for an lvpecl driver. this is a standard lvpecl termination with one s ide of the driver feeding the osci input. it is recommended that al l components in the schematics be placed in the layout. though so me components might not b e used, they can be utilized for debuggin g purposes. the datasheet specifications are characterized and guaranteed by using a quart z crystal as the input. figure 5a. general diagram for l vcmos driver to xtal input inte rface figure 5b. general d iagram for lvpecl driver to xtal input inte rface lvcmos_driver zo = 50 rs zo = ro + rs ro r2 100 r1 100 vcc osco osci c1 0.1 f lvpecl_driver zo = 50 r2 50 r3 50 c2 0.1 f osco osci zo = 50 r1 50 56 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet : l u l q j w k h ' l i i h u h q w l d o , q s x w w r $ f f h s w 6 l q j o h ( q g h g / h y h o v figure 6 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be l ocated as close to the input pin as possible. the ratio of r1 and r2 migh t need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the sum of the o utput impedance of the driver (ro) and the series resistance (rs) equ als the transmission line impedance. in addition, matched terminati on at the input will attenuate the sig nal in half. this can be done i n one of two ways. first, r3 and r4 in parallel should equal the transmi ssion line impedance. for most 50 w applications, r3 and r4 can be 100 w . the values of the resistors can be increased to reduce the load ing for slower and weaker lvcmos dr iver. when usin g single-ended signaling, the noise rejection benefits of differential signali ng are reduced. even though the differ ential input can handle full rai l lvcmos signaling, it is reco mmended that the amplitude be reduced. the datasheet specifies a lower differential amplitude , however this only applies to dif ferential signals. for single-e nded applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. suggest edge rate faster than 1v/ns. though some of the recommended components might not b e used, the pads shou ld be placed in the layout. they can be utilized for debugging purposes. the datash eet specifications are characteri zed and guaranteed by using a differential signal. figure 6. recommended schematic for wiring a differential inpu t to accept single-ended levels 57 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 3.3v differential cl ock input interface clkx/nclkx accepts lvds, lvpec l, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 7a to figure 7e show interface examples for the clkx/nclkx in put driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor o f the driver component to confi rm the driver termination requirements. for example, in figure 7a , the input termination applies for idt open e mitter lvhstl drivers. if you are using an lvhstl driver from anot her vendor, use their terminati on recommendation. figure 7a. clkx/nclkx input driven by an ? idt open emitter lvhstl driver figure 7b. clkx/nclkx input driven by a ? 3.3v lvpecl driver figure 7c. clkx/nclkx input driven by a ? 3.3v hcsl driver figure 7d. clkx/nclkx input driven by a ? 3.3v lvpecl driver figure 7e. clkx/nclkx input driven by a ? 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input hcsl *r3 *r4 clk nclk 3.3v 3.3v differential input 58 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 2.5v differential cl ock input interface clkx/nclkx accepts lvds, lvpecl, lvhstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 8a to figure 8d show interface examples for the clkx/nclkx input driven by the most common driver types. th e input interfaces sugges ted here are examples only. please consu lt with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 8a , the input termination applies for idt open e mitter lvhstl drivers. if you are using an lvhstl driver from anot her vendor, use their terminati on recommendation. figure 8a. clkx/nclkx input driven by an ? idt open emitter lvhstl driver figure 8b. clkx/nclkx input driven by a ? 2.5v lvpecl driver figure 8c. clkx/nclkx input driven by a ? 2.5v lvpecl driver figure 8d. clkx/nclkx input driven by a ? 2.5v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 2.5v lvhstl idt open emitter lvhstl driver differential input 59 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet recommendations for unused input and output pins i nputs: clkx/nclkx input for applications not requiring t he use one or more reference cl ock inputs, both clkx and nclkx can be left floating. though not required, but for addit ional protection, a 1k ? resistor can be tied from clkx to ground. it is recommended that clkx, nclkx not be drive n with active signals when not enabled for use. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional prot ection. a 1k ? resistor can be used. outputs: lvpecl outputs any unused lvpecl ou tput pairs can be left floating. we recommend that there is no trac e attached. both sides of the differential output pair should either be left floating or term inated. lvds outputs any unused lvds output pairs c an be either left floating or terminated with 100 ? across. if they are left floating there should be no trace attached. lvcmos outputs any lvcmos output c an be left floating if unused. there should be no trace attached. termination for 3. 3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two diff erent layouts mentioned are recommended only as guidelines. the differential outputs generate ecl/lvpecl compatible outputs . therefore, terminating resistors (dc curren t path to ground) or current sources must be used for functionality. these outputs a re designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 9a and figure 9b show two different layouts which are reco mmended only as gu idelines. oth er suitable clock layouts may exist and it would be recommended th at the board designers simulate to g uarantee compatibility across all printed circuit and clock co mponent process variations. figure 9a. 3.3v lvpecl output ter mination figure 9b. 3.3v lvpecl o utput termination r1 84 r2 84 3.3v r3 125 r4 125 z o = 50 z o = 50 inp ut 3.3v 3 .3v + _ 60 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet termination for 2. 5v lvpecl outputs figure 10a and figure 10c show examples of te rmination for 2.5v lvpecl driver. these terminatio ns are equivalent to terminating 50 ? to v cco C 2v. for v cco = 2.5v, the v cco C 2v is very close to ground level. the r3 in figure 10c can be eliminated and the termination is shown in figure 10b . figure 10a. 2.5v lvpecl dr iver termination example figure 10b. 2.5v lvpecl driv er termination example figure 10c. 2.5v lvpecl driv er termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 50 r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 50 r1 50 r2 50 r3 18 + ? 61 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 2.5v and 3.3v hcsl recommended termination figure 11a is the recommended source t ermination for applications where the driver and receiver w ill be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 impedance single-ended or 100 differential. figure 11a. recommended sourc e termination (where the driver a nd receiver will be on separate pcbs) figure 11b is the recommended termination for applications where a point-to-point connection can be used. a point-to-point connect ion contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflecti ons will be minimized. in addition, a seri es resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the optio nal resistor can range from 0 to 33 . all traces should be 50 impedance single-ended or 100 differential. figure 11b. recommended termination (where a point-to-point con nection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt 62 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet / 9 ' 6 ' u l y h u 7 h u p l q d w l r q for a general lvds in terface, the recommended value for the termination impedance (z t ) is between 90 w and 132 w . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design us es a 100 w parallel resistor at the receiver and a 100 w differential transmission-line environmen t. in order to avoid any transmission-line reflection i ssues, the comp onents should be surface mounted and mu st be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in can be used with either type of output structure. , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor val ue should be approximately 50pf. if using a non-standard terminati on, it is recommended to contact idt a nd confirm if the output structu re is current source or voltage source type. in addition, since these outputs are lvds compatible, th e input receivers amplitude and common-mode input range should be verified for compatibility wi th the output. figure 12a. standard lvds termination figure 12b. optional lvds termination 63 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a la nd pattern must be incorporated on the printed circuit board (pcb) within the footprint of the pac kage corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 13 . the solderable area on the pcb, as defined by the solder mask, shoul d be at least the same size/sh ape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of t he land pattern and the inner edges of pad pattern for the leads to avoid any s horts. while the land pattern on the pcb provides a means of heat tran sfer and electrical grounding from t he package to the board through a solder joint, thermal vias are n ecessary to effe ctively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as hea t pipes. the number of vias (i.e. heat pipes) are application specific and dependent upon the package power dissipation as well as electrical conductivity require ments. thus, thermal and electri cal analysis and/or testing are recommended to determine the minimu m number needed. maximum thermal an d electrical performance is achieved when an array of vias is incorporated in the land patt ern. it is recommended to use as many v ias connected to ground as possible. it is also recommend ed that the via diameter should b e 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wi cking inside the via during the soldering process whic h may result in void s in solder between t he exposed pad/slug and the therma l land. precautions should be ta ken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recomm endations are to be used as a guideline only. for further information, please refer to the ap plication note on the surface mount a ssembly of amkors thermally/ electrically enhance lead frame base package, amkor technology. figure 13. p.c. assemb ly for exposed pad t hermal release path C side view (drawing not to scale) schematic and layout information schematics for 8t49n287 can be found on idt.com. please search for the 8t49n287 device and click on the link for evaluation bo ard schematics. crystal recommendation this device was vali dated using fox 277lf s eries through-hole crystals including part #277lf-4 0-18 (40mhz) and #277lf-38.88-2 (38.88mhz). if a surf ace mount crystal is desired, we recommend fox part #603-40-48 (40mhz) or #603-38.88- 7 (38.88mhz). i 2 c serial eeprom recommendation the 8t49n287 was designed to operate with most standard i 2 c serial eeproms of 256 bytes or la rger. atmel at24c04c was used during device characterization an d is recommended for use. plea se contact idt for review of any other i 2 c eeproms compatibility with the 8t49n287. solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via 64 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 3 & , ( [ s u h v v $ s s o l f d w l r q 1 r w h pci express jitter analysis m ethodology models the system response to reference clock jitt er. the block diagram below sho ws the most frequently used in which a copy of the reference clock is p rovided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serd es plls are modeled as well as the phase interpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: ht s () h3 s () h1 s () h2 s () C [] = the jitter spectrum seen by the receiver is the result of apply ing this system transfer function to t he clock spectrum x(s) and is: ys () xs () h3 s () h1 s () h2 s () C [] = in order to generate time domain jitter numbers, an inverse fou rier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the entire spectrum: dc to nyquist (e.g., for a 100mhz reference clock: 0hz C 50mhz) and the jitter resul t is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functi ons are defined with 2 evaluation ranges and the final ji tter number is reported in rm s. the two evaluation ranges for pci express gen 2 are 10khz C 1.5mhz (low band) and 1.5mhz C nyquist (high band). the plots show the individual transfer functions as well as the overall transfer f unction ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of t ransfer function for pci express gen 3 , one transfer functi on is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are differ ent from gen 1 and the jitter res ult is reported in rms. pcie gen 3 magnitude of transfer function for a more thorough overview o f pci express jitter analysis methodology, please refer to idt application note 65 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet 3 r z h u ' l v v l s d w l r q d q g 7 k h u p d o & r q v l g h u d w l r q v the 8t49n287 is a multi-functio nal, high speed dev ice that targ ets a wide variety of clock freq uencies and applications. since this device is highly programmable with a bro ad range of features and function ality, the power consumption will vary as each of these features and functions is enabled. the 8t49n287 device was designe d and cha racteriz ed to operate w ithin the ambient industrial tem perature range of -40c to +85 c. the ambient temperature represents t he temperature around the device, not the junction temperature . when using the device in extre me cases, such as maximum operating frequency and high ambient temperatur e, external air flow may be required in order to ensure a safe and reliable junction temperature. extreme care must be t aken to avoid excee ding 125c junction temperature. the power calculation examples below were generated using a max i mum ambient temperature and supply voltage. for many applicati ons, the power consumption will be much low er. please contact idt techni cal support for any concerns on calculating the power dissipation for your own specific configuration. power domains the 8t49n287 device has a number of separate power domains that can be independently enabled and disabled via register accesse s (all power supply pins must still be connected to a valid supply vol tage). figure 14 below indicates the individual domains and the associated powe r pins. /[y l 5 . / // 5 t[[ // / // 5 t[[ // / // h 5 . v // h h 5 . v // h h 5 . v // h h 5 . v // h h 5 . v // h h 5 . v // h h 5 . v // h h 5 . v // h figure 14. 8t49n287 power domains for the output paths shown above, there are three different str uctures that are used. q0 and q1 use one output path structure, q2 and q3 use a second structure and q[4:7] use a 3 rd structure. power consumption data will vary slightly depending on the structure used as shown in the appropriate tables below. power consumption calculation determining total power consump tion involves several steps: 1. determine the power consumptio n using maximum current values for core and analog voltage supplies from and . 2. determine the nominal power consumptio n of each enabled outpu t path. a. this consists of a base am ount of p ower that is independent of operating frequency, as shown in through (depending on the chosen output protocol). b. then there is a variable amount o f power that is related to the output frequency. this can be determined by multiplying the output frequency by the fq_factor shown in through . 3. all of the above totals are then summed. 66 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet thermal considerations once the total power consumption has been determined, it is nec essary to calculate the maximum operating junction temperature for the device under the environmental conditions it will operate in. thermal conduction paths, air flow rate and ambient air temperature are factors that can affect this. the thermal conduct ion path refers to whether heat is to be conducted away via a h eatsink, via air flow or via con duction into the pcb through the device pads (including the epad). thermal condu ction data is provided for typical scenarios in table 14 below. please contact idt for assistance in calculatin g results under other scenarios . table 14. thermal resistance ? ja for 56-lead vfqfn, forced convection current consumption data and equations table 15a. 3.3v lvpecl ou tput calcula tion table table 15b. 3.3v hcsl out put calculation table table 15c. 3.3v lvds o utput calculation table table 15d. 2.5v lvpecl ou tput calculation table table 15e. 2.5v hcsl out put calculation table table 15f. 2.5v lvds o utput calculation table ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 16.0c/w 12.14c/w 11. 02c/w output fq_factor (ma/mhz) base current (ma) q0 0.00593 40.1 q1 q2 0.01363 63.8 q3 q4 0.00591 42.9 q5 q6 q7 output fq_factor (ma/mhz) base current (ma) q0 0.00582 40.1 q1 q2 0.01358 63.8 q3 q4 0.00553 43.1 q5 q6 q7 output fq_factor (ma/mhz) base current (ma) q0 0.00627 48.6 q1 q2 0.01404 72.5 q3 q4 0.00630 51.3 q5 q6 q7 output fq_factor (ma/mhz) base current (ma) q0 0.00373 32.8 q1 q2 0.01134 56.5 q3 q4 0.00369 35.7 q5 q6 q7 output fq_factor (ma/mhz) base current (ma) q0 0.00354 32.9 q1 q2 0.01125 56.5 q3 q4 0.00353 35.7 q5 q6 q7 output fq_factor (ma/mhz) base current (ma) q0 0.00366 40.8 q1 q2 0.01148 64.5 q3 q4 0.00367 43.7 q5 q6 q7 67 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet table 15g. 3.3v lvcmos ou tput calculation table table 15h. 2.5v lvcmos o utput calculation table table 15i. 1.8v lvcmos o utput calculation table applying the values t o the following equat ion will yield output current by frequency: qx current (ma) = fq_factor * frequency (mhz) + base current where: qx current is the specific out put current according to output type and fr equency fq_factor is used for calculat ing current increase due to output frequenc y base current is the base current for each output path ind ependent of output frequency the second step is to multiply the power dissipated by the ther mal impedance to determine the maximum power gradient, using th e following equation: t j = t a + ( ? ja * pd total ) where: t j is the junction temperature (c) t a is the ambient temperature (c) ? ja is the thermal resi stance value from table 14 , dependent on ambient airflow (c/w) pd total is the total power dissipation of the 8t49n287 under usage con ditions, including power dissipated due to loading (w) note that the power dissipation per output pair due to loading is assumed to be 27.95mw for lvpe cl outputs and 44.5mw for hcsl outputs. when selecting lvcmos outputs, power dissipation through the lo ad will vary based on a variety of factors including terminatio n type and trace length. for these examples, pow er dissipation through loading w ill be calculated using c pd (found in table 2 ) and output frequency: pd out = c pd * f out * v cco 2 where: pd out is the power dissipat ion of the output (w) cpd is the power dissipat ion capacitance (pf) fout is the output frequency of the selected output (mhz) v cco is the voltage supplied to the appropriate output (v) output base current (ma) q0 37.4 q1 q2 61.6 q3 q4 40.6 q5 q6 q7 output base current (ma) q0 30.8 q1 q2 54.8 q3 q4 33.7 q5 q6 q7 output base current (ma) q0 27.4 q1 q2 51.4 q3 q4 30.3 q5 q6 q7 68 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet ( [ d p s o h & d o f x o d w l r q v ( [ d p s o h & r p p r q & x v w r p h u & r q i l j x u d w l r q 9 & r u h 9 r o w d j h 2 x w s x w 2 x w s x w 7 \ s h ) u h t x h q f \ 0 + ] 9 & & 2 q0 lvpecl 245.76 3.3 q1 lvpecl 245.76 3.3 q2 lvpecl 33.333 3.3 q3 lvpecl 33.333 3.3 q4 lvds 125 3.3 q5 lvds 125 3.3 q6 lvcmos 25 3.3 q7 lvcmos 25 3.3 pll0 enabled pll1 enabled ? core supply current, i cc = 100ma (max) ? analog supply current, i cca = 265ma (max) q0 current = 0.00593x 245 .76 + 40.1 = 41.56ma q1 current = 0.00593x 245 .76 + 40.1 = 41.56ma q2 current = 0.01363x 33.333 + 63. 8 = 64.25ma q3 current = 0.01363x 33.333 + 63. 8 = 64.25ma q4 current = 0.00630x 125 + 51.3 = 52.09ma q5 current = 0.00630x 125 + 51.3 = 52.09ma q6 current = 40.6ma q7 current = 40.6ma ? total output current = 3 97ma (max) total device current = 100ma + 265ma + 397ma = 762 ma total device power = 3.465v * 762ma = 264 0.3mw ? power dissipated through output loading: lvpecl = 27.95mw * 4 = 111 .8mw lvds = already accounted for in de vice power hcsl = n/a lvcmos = 14.5pf * 25mhz * 3.465v 2 * 2 output pairs = 8.7mw ? total power = 2640.3m w + 111.8mw + 8.7mw = 2760.8mw or 2.8w with an ambient tempera ture of 8 5c and no airflow, the junctio n temperature is: t j = 85c + 16.1 c/w * 2.8w = 130.1c this junction temperature is above the maximum allowable. in in stances where maximum junction te mperature is exceeded adjustme nts need to be made to either airflow or ambient temperatu re. in this ca se, adjusting airflow to 1m/s ( q ja = 12.4c/w) will reduce junction temperature to 119.7c. if no airflow adjustm ents can be made, the maximum a mbient operating temper ature must be reduced by a minimum of 5.1c. 69 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet ( [ d p s o h + l j k ) u h t x h q f \ & x v w r p h u & r q i l j x u d w l r q 9 & r u h 9 r o w d j h 2 x w s x w 2 x w s x w 7 \ s h ) u h t x h q f \ 0 + ] 9 & & 2 q0 lvds 625.00 2.5 q1 lvds 625.00 2.5 q2 lvpecl 161.133 2.5 q3 lvpecl 161.133 2.5 q4 hcsl 25 3.3 q5 hcsl 25 3.3 q6 hcsl 125 3.3 q7 hcsl 156.25 3.3 pll0 enabled pll1 disabled ? core supply current, i cc = 100ma (max) ? analog supply current, i cca = 187ma (max, pll0 path only) q0 current = 0.00366x 625 + 40.8 = 43.09ma q1 current = 0.00366x 625 + 40.8 = 43.09ma q2 current = 0.01134x 161.13 3 + 56. 5 = 58.3ma q3 current = 0.01134x 161.13 3 + 56. 5 = 58.3ma q4 current = 0.00553x 25 + 43 .1 = 43.24ma q5 current = 0.00553x 25 + 43 .1 = 43.24ma q6 current = 0.00553x 125 + 43.1 = 43.79ma q7 current = 0.00553x 156 .25 + 43.1 = 43.96ma ? total output current = 202.8ma (v cco = 2.5v), 174.23ma (v cco = 3.3v) total device power = 3.465v *(100 ma + 187ma + 174.23ma) + 2.625 v * 202.8ma = 2130.5mw ? power dissipated through output loading: lvpecl = 27.95mw * 2 = 55 .9mw lvds = already accounted for in de vice power hcsl = 44.5mw * 4 = 178mw lvcmos = n/a total power = 2130.5m w + 55 .9mw + 178mw = 2364.4mw or 2.36w with an ambient tempera ture of 85c, the ju nction temperature i s: t j = 85c + 16.1c/w *2.36w = 123c this junction temperature is b e low the maximum allowable. 70 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet ( [ d p s o h / r z 3 r z h u & x v w r p h u & r q i l j x u d w l r q 9 & r u h 9 r o w d j h 2 x w s x w 2 x w s x w 7 \ s h ) u h t x h q f \ 0 + ] 9 & & 2 q0 lvds 156.25 2.5 q1 lvds 156.25 2.5 q2 lvds 161.133 2.5 q3 lvcmos 33.333 1.8 q4 lvcmos 25 1.8 q5 lvcmos 25 1.8 q6 lvcmos 25 1.8 q7 lvds 156.25 2.5 pll0 enabled pll1 enabled ? core supply current, i cc = 95ma (max) ? analog supply current, i cca = 260ma (max) q0 current = 0.00366x 156 .25 + 40.8 = 41.37ma q1 current = 0.00366x 156 .25 + 40.8 = 41.37ma q2 current = 0.01148x 161.13 3 + 64.5 = 66.35ma q3 current = 51.4ma q4 current = 30.3ma q5 current = 30.3ma q6 current = 30.3ma q7 current = 0.00367x 156 .25 + 43.7 = 44.27ma ? total output current = 1 93.36ma (v cco = 2.5v), 142.3ma (v cco = 1.8v) total device power = 2.625v *(95m a + 260ma + 193.36ma) + 1.89v * 142.3ma = 1708.4mw ? power dissipated through output loading: lvpecl = n/a lvds = already accounted for in de vice power hcsl = n/a lvcmos_33.3mhz = 17pf * 33.3mhz * 1.8 9v 2 * 1 output pair = 2.02mw lvcmos_25mhz = 12. 5p f * 25mhz * 1.89v 2 * 3 output pairs = 3.35mw total power = 1708.4mw + 2.02 mw + 3.35mw = 1714mw or 1.7w with an ambient tempera ture of 85c, the junction temperature i s: t j = 85c + 16.1c/w *1.7w = 112.4c this junction temperature is be low the maximum allowable. 71 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet reliability information table 16. ? ja vs. air flow table for a 56-lead vfqfn note: theta ja ( ? ja )values calculated using a 4-lay er jedec pcb (114.3mm x 101.6mm ), with 2oz. (70m) copper plating on all 4 layers. transistor count the transistor count f or 8t49n287 is: 998,958 package outline drawings the package outline drawings are located at the end of this document. the package information is the most current data availabl e and is subject to change without notice or revision of this document. ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard test boards 16.0c/w 12.14c/w 11. 02c/w 72 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet marking diagram ordering information table 17. ordering information note: for the specific, publicly available -ddd order codes, re fer to femtoclock ng universal frequency translator ordering product information document. for custom -ddd orde r codes, please contact idt for more information. table 18. pin 1 orientation in tape and reel packaging 1. line 1 and line 2 is the part number. 2. ?ddd? denotes a configuration-specific number (dash code). 3. # denotes stepping. 4. ?yyww? denotes: ?yy? is the last two digits of the year, and ?ww? is the work week number ? that the part was assembled. 5. ?$? denotes the mark code. 3 d u w 2 u g h u 1 x p e h u 0 d u n l q j 3 d f n d j h 6 k l s s l q j 3 d f n d j l q j 7 h p s h u d w x u h 8t49n287a-dddnlgi idt8t49n287a-dddnlgi 56-lead vfqfn, lead-free tr ay -40 ? c to +85 ? c 8t49n287a-dddnlgi8 idt8t49n287a-dddnlgi 56-lead vfqfn, lead-free tape & reel, pin 1 orientation: eia-481-c -40 ? c to +85 ? c 8t49n287a-dddnlgi# idt8t49n287a-dddnlgi 56-lead vfqfn, lead-free tape & reel, pin 1 orientation: eia-481-d -40 ? c to +85 ? c part number suffix pin 1 o rientation illustration nlgi8 quadrant 1 (eia-481-c) nlgi# quadrant 2 (eia-481-d) user direction of feed correct pin 1 orientation carrier tape topside (round sprocket holes) user direction of feed correct pin 1 orientation carrier tape topside (round sprocket holes) disclaimer integrated device technology, inc. (idt) and its affiliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specificati ons described herein at any time, without notice, at idt?s sole discreti on. performance specifications and operating param eters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provi ded without representation or wa rranty of any kind, whether expr ess or implied, including, bu t not limited to, the suitabil ity of idt's products for any particular purpose, an implied warranty of merchantability, or non-infringement of t he intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malf unction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and othe r countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossa ry of common terms, visit www.idt.com/go/glossary . integrated device technology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 73 ?2018 integrated device technology, inc. january 31, 2018 8t49n287 datasheet revision history revision date description of change january 31, 2018 updated i2c mode operation to indicate support for v2. 1 of the i2c specification october 30, 2017 added a marking diagram september 11, 2017 ? added a note before digital pll0 status register bit field locations and descriptio ns and digital pll1 status register bit field locations and descriptions ? added the following fields to digital pll0 status register bit field locations and descriptio ns and digital pll1 status register bit field locations and descriptions : no_ref, sm_sts, and plllck october 27, 2016 crystal recommendation - deleted idt crystal reference. february 1, 2016 t17, per pcn# w1512-01, effective date 03/18/2016 - changed part/ord er number from 8t49n287-dddnlgi to 8t49n287a-dddnlgi, and ? marking from idt8t49n287-dddnlgi to idt8t49n287a-dddnlgi. updated datasheet header/footer. july 9, 2015 device start-up and reset behavior - added second paragraph. june 1, 2015 ac characteristics table - added f out minimum parameters. termination for 3.3 v lvpecl outputs updated figure 9a. updated crystal recommendation . march 20, 2015 table 11a , ac characteristics table - upd ated lvds rise/fall time maximu m spec. from 500 to 400ps. miscellaneous content enhancement in: output phase control on switchover section; table 6a , table 6c , table 6e and table 6g , and pin assignment format. november 6, 2014 description - first paragraph/last sentence, added hcsl. features - added hcsl in accept s up to two lvpec l.... bullet and generates 8 lvpecl... bullet. |
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